Rescheduling a load instruction based on past replays
Rescheduling a load instruction based on past replays is disclosed. A load replay predictor of a processor device determines, at a first time, that a load instruction is scheduled to be executed by a load store unit to load data from a memory location. The load replay predictor accesses load replay data associated with a previous replay of the load instruction and, based on the load replay data, causes the load instruction to be rescheduled.
1. A method comprising:
receiving, by a load store unit of a processor device, a load instruction to load data from a memory location, the load instruction identified in a cache line of a cache memory, the cache line comprising one or more processor instructions and cache line metadata associated with the one or more processor instructions, the one or more processor instructions comprising the load instruction;
determining at a first time, by a load replay predictor of the processor device, that the load instruction is scheduled to be executed by the load store unit;
accessing, by the load replay predictor from the cache line metadata, load replay data associated with a previous replay of the load instruction;
based on the load replay data, causing, by the load replay predictor, the load instruction to be rescheduled for subsequent execution;
sending, by the load replay predictor to the load store unit, a first message indicating that the load instruction is not to be executed;
in response to causing the load instruction to be rescheduled for subsequent execution, causing, by the processor device at a second time subsequent to the first time, execution of the load instruction;
receiving, by the load replay predictor from a component of the processor device, a second message indicating that the load instruction was executed, wherein the second message comprises a memory address from which the load instruction is to load the data; and
based on the second message, updating, by the load replay predictor, the load replay data to indicate that the load instruction was executed.
2. The method of claim 1 wherein the load instruction is a programmatic instruction from an executable program.
3. The method of claim 1 wherein the load instruction is an internal load instruction generated by the processor device.
4. The method of claim 1 further comprising:
determining, at a time prior to the first time, that the load instruction is scheduled to be executed to load the data from the memory location;
executing the load instruction to load the data from the memory location;
subsequently determining that the load instruction must be replayed; and
generating the load replay data based on determining that the load instruction must be replayed.
5. The method of claim 4 further comprising:
storing, by the load replay predictor, the load replay data in the cache line metadata that corresponds to the load instruction.
6. A processor device comprising:
a load store unit to:
receive a load instruction to load data from a memory location, the load instruction identified in a cache line of a cache memory, the cache line comprising one or more processor instructions and cache line metadata associated with the one or more processor instructions, the one or more processor instructions comprising the load instruction; and
a load replay predictor to:
determine, at a first time, that the load instruction is scheduled to be executed by the load store unit;
access, from the cache line metadata, load replay data associated with a previous replay of the load instruction;
based on the load replay data, cause the load instruction to be rescheduled for subsequent execution;
send, to the load store unit, a first message indicating that the load instruction is not to be executed;
in response to causing the load instruction to be rescheduled for subsequent execution, cause, at a second time subsequent to the first time, execution of the load instruction;
receive, from a component of the processor device, a second message indicating that the load instruction was executed, wherein the second message comprises a memory address from which the load instruction is to load the data; and
based on the second message, update the load replay data to indicate that the load instruction was executed.
7. The processor device of claim 6 wherein the load instruction is a programmatic instruction from an executable program.
8. The processor device of claim 6 wherein the load replay predictor is further to:
determine, at a time prior to the first time, that the load instruction is scheduled to be executed to load the data from the memory location;
execute the load instruction to load the data from the memory location;
subsequently determine that the load instruction must be replayed; and
generate the load replay data based on determining that the load instruction must be replayed.
9. The processor device of claim 8 wherein the load replay predictor is further to:
store the load replay data in the cache line metadata that corresponds to the load instruction.
10. A non-transitory computer-readable storage medium including executable instructions to cause a processor device to:
receive, by a load store unit of the processor device, a load instruction to load data from a memory location, the load instruction identified in a cache line of a cache memory, the cache line comprising one or more processor instructions and cache line metadata associated with the one or more processor instructions, the one or more processor instructions comprising the load instruction;
determining at a first time, by a load replay predictor of the processor device, that the load instruction is scheduled to be executed by the load store unit;
accessing, by the load replay predictor from the cache line metadata, load replay data associated with a previous replay of the load instruction;
based on the load replay data, causing, by the load replay predictor, the load instruction to be rescheduled for subsequent execution;
sending, by the load replay predictor to the load store unit, a first message indicating that the load instruction is not to be executed;
in response to causing the load instruction to be rescheduled for subsequent execution, causing, by the processor device at a second time subsequent to the first time, execution of the load instruction;
receiving, by the load replay predictor from a component of the processor device, a second message indicating that the load instruction was executed, wherein the second message comprises a memory address from which the load instruction is to load the data; and
based on the second message, updating, by the load replay predictor, the load replay data to indicate that the load instruction was executed.
11. The non-transitory computer-readable storage medium of claim 10 , wherein the load instruction is a programmatic instruction from an executable program.