IP Library Granted Patent US 11,404,079
Granted Patent B1
US 11,404,079 · App. 17/242,013 · Granted Aug 2, 2022

Data storage device writing to defective data sector for fly height control

Inventors: Joey M. Poss (Rochester, MN); Naoto Ito (Kanagawa, JP); Phillip S. Haralson (Huntington Beach, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G11B5/6011
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Quick Facts
Patent No.
US 11,404,079
App. No.
17/242,013
Granted
Aug 2, 2022
Kind
B1
Abstract

A data storage device is disclosed comprising a head actuated over a magnetic media. A write operation is executed to a first data sector by writing to at least part of a defective data sector preceding the first data sector in order to achieve a target fly height of the head prior to writing to the first data sector.

Claims (56)

1. A data storage device comprising:

a magnetic media;

a head actuated over the magnetic media, the head comprising a write coil; and

control circuitry configured to execute a write operation to a first data sector by:

applying a write current to the write coil at a first maximum transition frequency to write to at least part of a defective data sector preceding the first data sector in order to achieve a target fly height of the head prior to writing to the first data sector; and

applying the write current to the write coil at a second maximum transition frequency to write to the first data sector, the second maximum transition frequency being higher than the first maximum transition frequency.

2. The data storage device as recited in claim 1 , wherein:

the head further comprises an energy assist element; and

the control circuitry is further configured to write to at least part of the defective data sector by applying the write current to the write coil and a write bias to the energy assist element.

3. The data storage device as recited in claim 1 , wherein the control circuitry comprises a preamp circuit configured to generate the write current, wherein the preamp circuit is configured to receive a command to write to at least part of the defective data sector.

4. The data storage device as recited in claim 3 , wherein the preamp circuit comprises a serial interface configured to receive the command.

5. A data storage device comprising:

a magnetic media;

a head actuated over the magnetic media, the head comprising a write coil; and

control circuitry configured to:

execute a write operation to a first data sector by writing to at least part of a defective data sector preceding the first data sector in order to achieve a target fly height of the head prior to writing to the first data sector; and

write to at least part of the defective data sector by applying a write current to the write coil,

wherein:

the control circuitry comprises a preamp circuit configured to generate the write current,

the preamp circuit is configured to receive a command to write to at least part of the defective data sector, and

the preamp circuit comprises an oscillator configured to generate an oscillating write current used to write to at least part of the defective data sector.

6. A data storage device comprising:

a magnetic media;

a head actuated over the magnetic media, wherein the head comprises a write coil;

a preamp circuit configured to apply a write current to the write coil; and

control circuitry configured to execute a write operation to a first data sector by transmitting a command to the preamp circuit in order to write to at least part of a defective data sector preceding the first data sector in order to achieve a target fly height of the head prior to writing to the first data sector, wherein the preamp circuit comprises an oscillator configured to generate an oscillating write current used to write to at least part of the defective data sector.

7. The data storage device as recited in claim 6 , wherein the preamp circuit is further configured to write to at least part of the defective data sector by applying the write current to the write coil.

8. The data storage device as recited in claim 7 , wherein:

the head further comprises an energy assist element; and

the preamp circuit is further configured to write to at least part of the defective data sector by applying the write current to the write coil and a write bias to the energy assist element.

9. The data storage device as recited in claim 6 , wherein the preamp circuit comprises a serial interface configured to receive the command.

10. A preamp circuit comprising:

a write amplifier configured to generate a write current for a write coil of a head;

an interface configured to receive a write signal;

an oscillator configured to generate an oscillating signal; and

write control logic configured to:

while the head is over a defective data sector, apply the oscillating signal to the write amplifier in order to write to at least part of the defective data sector; and

while writing to a first data sector following the defective data sector, apply the write signal to the write amplifier.

11. The preamp circuit as recited in claim 10 , wherein the write control logic is further configured to apply a write bias to a write assist element of the head while the head is over the defective data sector in order to write to at least part of the defective data sector.

12. The preamp circuit as recited in claim 10 , wherein:

the interface further comprises a write/read line, a mode line, and a serial input/output (SIO) interface configured to receive a mode control command;

the write control logic configures an operating mode of the mode line in response to the mode control command; and

when configured into a defective data sector write mode, the write control logic configures a gain of the write amplifier based on the mode line.

13. The data storage device as recited in claim 1 , wherein the control circuitry is further configured to:

initially set an amplitude of the write current for the at least part of the defective data sector higher than an amplitude of the write current for the first data sector; and

then ramp down the write current for the at least part of the defective data sector to the same amplitude as the write current for the first data sector.

14. The data storage device as recited in claim 1 , wherein the control circuitry is further configured to:

initially set an amplitude of the write current for the at least part of the defective data sector higher than an amplitude of the write current for the first data sector; and

then ramp down the write current for the at least part of the defective data sector to zero.

15. The data storage device as recited in claim 1 , wherein the control circuitry is further configured to:

disable the write current from being applied to the main pole while the head is over a servo sector between the defective data sector and the first data sector.

16. The data storage device as recited in claim 2 , wherein the control circuitry is further configured to:

start applying the write bias to the energy assist element while the head is over a servo sector preceding the at least part of the defective data sector.

17. The data storage device as recited in claim 2 , wherein the control circuitry is further configured to:

continue applying the write bias to the energy assist element while the head is over a servo sector between the defective data sector and the first data sector.

18. The data storage device as recited in claim 1 , wherein the defective data sector is not used to store user data.

Assignments (5)
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2021
From: POSS, JOEY M.; ITO, NAOTO; HARALSON, PHILLIP S.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 056060/0483 →