Three-dimensional integrated circuit (3D IC) power distribution network (PDN) capacitor integration

1. A three-dimensional (3D) integrated circuit (IC), comprising:

a first die directly coupled to a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) included in the first die;

a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die; and

active circuitry coupled to the 3D stacked capacitor through the PDN in the first die.

2. The 3D IC of claim 1 , further comprising a plurality of micro-bumps to connect the 3D stacked capacitor to the PDN in the first die.

3. The 3D IC of claim 1 , further comprising a plurality of micro-bumps to connect the second die to the PDN in the first die.

4. The 3D IC of claim 1 , in which the 3D stacked capacitor comprises a semiconductor die capacitor.

5. The 3D IC of claim 4 , in which the semiconductor die capacitor comprises:

a silicon substrate; and

a plurality of trench capacitors in the silicon substrate.

6. The 3D IC of claim 1 , in which the 3D stacked capacitor comprises an integrated passive device (IPD) capacitor die.

7. The 3D IC of claim 1 , in which the active circuitry is integrated within the first die.

8. The 3D IC of claim 1 , in which the PDN is proximate the first surface of the first die and directly coupled between the active circuitry and the 3D stacked capacitor.

9. The 3D IC of claim 1 , in which the active circuitry is coupled to the PDN proximate a second surface, distal from the first surface, of the first die and coupled to the 3D stacked capacitor through a plurality of vias.

10. The 3D IC of claim 1 , in which the PDN comprises a first PDN proximate the first surface of the first die, and a second PDN proximate a second surface, distal from the first surface, of the first die.

11. The 3D IC of claim 10 , further comprising a plurality of micro-bumps to connect the 3D stacked capacitor to the second PDN proximate the second surface of the first die.

12. The 3D IC of claim 10 , further comprising a plurality of micro-bumps to connect the second die to the second PDN proximate the second surface of the first die.

13. The 3D IC of claim 1 , further comprising a package substrate coupled to a second surface, distal from the first surface, of the first die through a plurality of package bumps.

14. A method for fabricating a three-dimensional (3D) integrated circuit (IC), comprising:

placing a 3D stacked capacitor directly on a first surface of a first die, the 3D stacked capacitor coupled to a power distribution network (PDN) included in the first die;

stacking a second die on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die; and

coupling active circuitry to the 3D stacked capacitor through the PDN in the first die.

15. The method of claim 14 , further comprising depositing a plurality of micro-bumps to connect the 3D stacked capacitor to the PDN in the first die.

16. The 3D IC of claim 14 , further comprising depositing a plurality of micro-bumps to connect the second die to the PDN in the first die.

17. The method of claim 14 , further comprises forming a plurality of trench capacitors in a silicon substrate to form the 3D stacked capacitor.

18. The method of claim 14 , further comprising integrating the active circuitry within the first die.

19. The method of claim 14 , further comprising:

forming the PDN proximate the first surface of the first die; and

directly coupling the PDN between the active circuitry and the 3D stacked capacitor.

20. The method of claim 14 , further comprising:

forming a first PDN proximate the first surface of the first die; and

forming a second PDN proximate a second surface, distal from the first surface, of the first die.