IP Library Granted Patent US 11,449,279
Granted Patent B1
US 11,449,279 · App. 17/242,992 · Granted Sep 20, 2022

Performance of a multi-core storage system

Inventors: Jianbin Kang (Beijing, CN); Geng Han (Beijing, CN); Vladimir Shveidel (Pardes-Hana, IL)
Assignee: EMC IP Holding Company LLC
G06F3/0659G06F3/0604G06F3/0683
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Quick Facts
Patent No.
US 11,449,279
App. No.
17/242,992
Granted
Sep 20, 2022
Kind
B1
Abstract

Techniques are used for improving performance of a storage system. The techniques may be used to provide, among other things, a set of counters for an object. Each counter corresponds to a unique processor in a multi-processor storage system. The state of a gate governing the object is determined. If the state of the gate is open, the counter corresponding to the first processor is incremented. The state of the gate for the object is re-determined. If the state of the gate remains open, the object is read and the counter corresponding to the first storage processor is decremented.

Claims (70)

1. A method comprising:

establishing, for an object, a set of counters, each counter corresponding to the object and a unique processor in a multi-processor storage system;

receiving, for a first processor, a request to read the object;

determining a state of a gate governing the object;

if the state of the gate is open, incrementing the counter corresponding to the first processor;

re-determining the state of the gate for the object;

if the state of the gate remains open, reading the object and decrementing the counter corresponding to the first storage processor.

2. The method of claim 1 , further comprising:

decrementing the counter corresponding to the first storage processor if the re-determining of the state of the gate indicates the gate is closed; and

repeating the step of determining the state of the gate of the object.

3. The method of claim 1 , further comprising:

receiving, for a second processor, a request to read the object;

determining the state of the gate governing the object;

if the state of the gate is open, incrementing the counter corresponding to the second processor;

re-determining the state of the gate for the object;

if the state of the gate remains open, reading the object and decrementing the counter corresponding to the second storage processor.

4. The method of claim 1 , further comprising:

receiving, for a second storage processor, a request to write to the object;

determining the state of the gate governing the object;

if the state of the gate is open, ensuring the gate is closed on behalf of the second storage processor;

determining that all of the requests to read the object have been completed; and

writing to the object.

5. The method of claim 4 , wherein determining that all of the requests to read the object have been completed comprises:

determining that all of the counters for the object have reached zero.

6. The method of claim 5 , wherein determining that all of the counters for the object have reached zero comprises:

continually comparing values of all of the counters for the object to zero until all of the values become zero.

7. The method of claim 4 , wherein determining that all of the requests to read the object have been completed comprises:

adding values of all of the counters for the object;

comparing the sum of the values to zero.

8. The method of claim 7 , further comprising:

repeating the steps of adding and comparing until the sum of the values of all of the counters equals zero.

9. The method of claim 4 , further comprising:

upon completion of the writing of the object, opening the gate.

10. The method of claim 4 , further comprising:

if the determining of the state of the gate indicates the gate is closed, repeating the step of determining the state of the gate of the object.

11. A system comprising at least one processor configured to:

establish, for an object, a set of counters, each counter corresponding to the object and a unique processor in a multi-processor storage system;

receive, for a first processor, a request to read the object;

determine a state of a gate governing the object;

if the state of the gate is open, increment the counter corresponding to the first processor;

re-determine the state of the gate for the object;

if the state of the gate remains open, read the object and decrement the counter corresponding to the first storage processor.

12. The system of claim 11 , wherein the at least one processor is further configured to:

decrement the counter corresponding to the first storage processor if the re-determination of the state of the gate indicates the gate is closed; and

continue to determine the state of the gate of the object.

13. The system of claim 11 , wherein the at least one processor is further configured to:

receive, for a second processor, a request to read the object;

determine the state of the gate governing the object;

if the state of the gate is open, increment the counter corresponding to the second processor;

re-determine the state of the gate for the object;

if the state of the gate remains open, read the object and decrement the counter corresponding to the second storage processor.

14. The system of claim 11 , wherein the at least one processor is further configured to:

receive, for a second storage processor, a request to write to the object;

determine the state of the gate governing the object;

if the state of the gate is open, ensure the gate is closed on behalf of the second storage processor;

determine that all of the requests to read the object have been completed; and

write to the object.

15. The system of claim 14 , wherein the at least one processor is further configured to:

determine that all of the counters for the object have reached zero.

16. The system of claim 15 , wherein the at least one processor is further configured to:

continually compare values of all of the counters for the object to zero until all of the values become zero.

17. The system of claim 14 , wherein the at least one processor is further configured to:

add values of all of the counters for the object;

compare the sum of the values to zero.

18. The system of claim 17 , wherein the at least one processor is further configured to:

continue to add the values of all of the counters and compare the sum until the sum equals zero.

19. The system of claim 14 , wherein the at least one processor is further configured to:

upon completion of the writing of the object, open the gate.

20. The system of claim 11 , wherein the at least one processor is further configured to:

repeat the step of determining the state of the gate of the object while the gate remains closed.

Assignments (10)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0280) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0255 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0124) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0012 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (056295/0001) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062021/0844 →
RELEASE OF SECURITY INTEREST Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 058297/0332 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0124 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 056295/0280 →
CORRECTIVE ASSIGNMENT TO CORRECT THE MISSING PATENTS THAT WERE ON THE ORIGINAL SCHEDULED SUBMITTED BUT NOT ENTERED PREVIOUSLY RECORDED AT REEL: 056250 FRAME: 0541. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 17, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 056311/0781 →
SECURITY AGREEMENT Recorded May 14, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 056250/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2021
From: KANG, JIANBIN; HAN, GENG; SHVEIDEL, VLADIMIR
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 056072/0180 →