Memory system and operating method thereof

1. A memory system comprising:

a memory device including a plurality of memory blocks; and

a memory controller for communicating with the memory device and controlling the memory device,

wherein the memory controller:

writes, when operating in a force unit access (FUA) mode, first write data requested to be written by a host to a buffer in the memory controller for temporarily storing data, which is to be written in the memory device, and a first memory block among the plurality of memory blocks,

writes, when the size of the data accumulatively stored in the buffer is greater than or equal to a size A which is a unit size of which data is written to a second memory block at a time among the plurality of memory blocks, second write data of the size A among the data stored in the buffer to the second memory block, and

controls the memory device so that an operation speed of the first memory block is set faster than an operation speed of the second memory block and a storage capacity of the first memory block is set smaller than a storage capacity of the second memory block,

wherein, when writing additional data to the first memory block is prohibited, the memory controller erases the first memory block after writing the data stored in the buffer to the second memory block.

2. The memory system of claim 1 , wherein the memory controller controls the memory device so that the first memory block is set as a single-level cell (SLC) memory block and the second memory block is set as a triple-level cell (TLC) memory block.

3. The memory system of claim 1 ,

further comprising an auxiliary built-in power unit for supplying power to the memory device and the memory controller when a sudden power loss (SPL) occurs,

wherein the memory controller monitors a charging time of the auxiliary built-in power unit and determines whether to operate in the force unit access mode based on the charging time of the auxiliary built-in power unit.

4. The memory system of claim 3 , wherein the memory controller monitors the charging time of the auxiliary built-in power unit at a time point when the memory system is booted or at every preset monitoring period.

5. The memory system of claim 1 , wherein, when the size of the first write data is less than a size B which is a unit size of which data is written to the first memory block at a time, the memory controller writes the first write data to the first memory block together with dummy data equal to a difference between the size B and the size of the first write data.

6. The memory system of claim 1 , wherein the memory controller first writes meta data corresponding to the first write data to the first memory block before writing the first write data to the first memory block.

7. An operating method of a memory system including a memory device with a plurality of memory blocks and a memory controller for communicating with the memory device and controlling the memory device comprising:

writing, by the memory controller, when operating in a force unit access (FUA) mode, first write data requested to be written by a host to a buffer in the memory controller for temporarily storing data, which is to be written in the memory device, and a first memory block among the plurality of memory blocks;

writing, by the memory controller, when the size of the data accumulatively stored in the buffer is greater than or equal to a size A which is a unit size of which data is written to a second memory block at a time among the plurality of memory blocks, second write data of the size A among the data stored in the buffer to the second memory block; and

controlling, by the memory controller, the memory device so that an operation speed of the first memory block is set faster than an operation speed of the second memory block and a storage capacity of the first memory block is set smaller than a storage capacity of the second memory block,

wherein, in response to writing additional data to the first memory block being prohibited, erasing, by the memory controller, the first memory block after writing the data stored in the buffer to the second memory block.

8. The operating method of claim 7 , further comprising:

monitoring, by the memory controller, a charging time of an auxiliary built-in power unit for supplying power to the memory device and the memory controller when a sudden power loss (SPL) occurs; and

determining, by the memory controller, whether to operate in the force unit access mode based on the charging time of the auxiliary built-in power unit.

9. The operating method of claim 7 , wherein the writing of the first write data to the buffer and the first memory block comprises writing, when the size of the first write data is less than a size B which is a unit size of which data is written to the first memory block at a time, the first write data to the first memory block together with dummy data equal to a difference between the size B and the size of the first write data.