High throughput storage encryption

1. A system on a chip (SoC) comprising:

a system microcontroller comprising processing circuitry configured to orchestrate operations on the SoC;

a security processor comprising processing circuitry configured to store a plurality of key-pairs to a key vault, each of the key-pairs having a first key and a second key, each of the key-pairs associated with one of a plurality of subsystems of the SoC;

a Direct Memory Access (DMA) engine comprising circuitry configured to receive, from a subsystem of the plurality of subsystems, storage access parameters identifying source data, a data size, and a destination storage address for a storage device; and

an encryption engine coupled to the DMA engine, the encryption engine comprising processing circuitry configured to:

determine a first tweak value based on a first sector address of the storage device, the first sector address based on the destination storage address;

encrypt the first tweak value according to the second key of the key-pair associated with the subsystem;

encrypt a first portion of the source data according to the first key of the key-pair associated with the subsystem and the encrypted first tweak value;

determine a second tweak value based on a second sector address of the storage device and encrypt the second tweak value according to the second key, wherein the second tweak value is determined and encrypted during encryption of the first portion of the source data and prior to completing encryption of the first portion of the source data; and

encrypt a second portion of the source data according to the first key and the encrypted second tweak value,

wherein the encryption engine comprises a plurality of interfaces, including:

a first interface to receive, from the system microcontroller, metadata describing a DMA transfer of the source data, the metadata comprising a block length, a sector address, and a key identifier (ID), and

a one-way second interface to receive the key-pair associated with the subsystem for storage in the key vault, and

wherein the key ID identifies a location of the key-pair associated with the subsystem in the key vault.

2. The SoC of claim 1 , further comprising a First-in, First-out (FIFO) queue configured to store a plurality of task records, each of the task records comprising a block length, a sector address, and the key ID, wherein the encryption engine obtains a task record from the FIFO queue to determine the first sector address and the key-pair.

3. The SoC of claim 1 , further comprising a configuration status register associated with the storage device, the configuration status register defining a sector size for the storage device, wherein the encryption engine utilizes the sector size to determine the second tweak value.

4. The SoC of claim 1 , wherein the encryption engine is configured to bypass encryption of the source data in response to a determination that the source data is not received over an Advanced eXtensible Interface (AXI) write channel.

5. The SoC of claim 1 , wherein the plurality of interfaces further include a third interface to receive the source data, and a fourth interface to output encrypted source data.

6. The SoC of claim 5 , wherein the third interface is communicatively coupled to the DMA engine.

7. The SoC of claim 1 , wherein the SoC is configured to support an artificial reality application.

8. The SoC of claim 1 , wherein the SoC is integrated into a peripheral device that is communicatively coupled to a head-mounted device (HMD).

9. The SoC of claim 1 , wherein the encryption engine is configured to receive the metadata via the first interface while concurrently transferring encrypted source data via a third interface of the plurality of interfaces, the third interface being different than the first interface.

10. An artificial reality system comprising:

a storage device;

a head mounted display (HMD) configured to output artificial reality content, the HMD including at least one system on a chip (SoC), wherein the at least one SoC comprises:

a security processor comprising processing circuitry configured to store a plurality of key-pairs to a key vault, each of the key-pairs having a first key and a second key, each of the key-pairs associated with one of a plurality of subsystems of the SoC;

a Direct Memory Access (DMA) engine comprising circuitry configured to receive, from a subsystem of the plurality of subsystems, storage access parameters identifying source data, a data size, and a destination storage address for the storage device; and

an encryption engine coupled to the DMA engine, the encryption engine comprising processing circuitry configured to:

determine a first tweak value based on a first sector address of the storage device, the first sector address based on the destination storage address;

encrypt the first tweak value according to the second key of the key-pair associated with the subsystem;

encrypt a first portion of the source data according to the first key of the key-pair associated with the subsystem and the encrypted first tweak value;

determine a second tweak value based on a second sector address of the storage device and encrypt the second tweak value according to the second key, wherein the second tweak value is determined and encrypted during encryption of the first portion of the source data and prior to completing encryption of the first portion of the source data; and

encrypt a second portion of the source data according to the first key and the encrypted second tweak value,

wherein the encryption engine comprises a plurality of interfaces, including:

a first interface to receive metadata describing a DMA transfer of the source data, the metadata comprising a block length, a sector address, and a key identifier (ID), and

a one-way second interface to receive the key-pair associated with the subsystem for storage in the key vault, and

wherein the key ID identifies a location of the key-pair associated with the subsystem in the key vault.

11. The artificial reality system of claim 10 , wherein the SoC further comprises a First-in, First-out (FIFO) queue configured to store a plurality of task records, each of the task records comprising a block length, a sector address, and the key ID, wherein the encryption engine obtains a task record from the FIFO queue to determine the first sector address and the key-pair.

12. The artificial reality system of claim 10 , wherein the SoC further comprises a configuration status register associated with the storage device, the configuration status register defining a sector size for the storage device, wherein the encryption engine utilizes the sector size to determine the second tweak value.

13. The artificial reality system of claim 10 , wherein the plurality of interfaces further include a third interface to receive the source data, and a fourth interface to output encrypted source data.

14. The artificial reality system of claim 10 , wherein the encryption engine is configured to receive the metadata via the first interface while concurrently transferring encrypted source data via a third interface of the plurality of interfaces, the third interface being different than the first interface.

15. A method comprising:

generating, by a security processor of a system on a chip (SoC), a plurality of key-pairs;

providing, by the security processor, the plurality of key-pairs to an encryption engine, wherein the encryption engine stores the plurality of key-pairs to a key vault, each of the key-pairs having a first key and a second key, each of the key-pairs associated with one of a plurality of subsystems of the SoC;

receiving, by a DMA engine and from a subsystem of the plurality of subsystems, storage access parameters identifying source data, a data size, and a destination storage address for a storage device;

receiving, by the encryption engine and via a first interface of the encryption engine, metadata describing a DMA transfer of the source data, the metadata comprising a block length, a sector address, and a key identifier (ID);

receiving, by the encryption engine and via a one-way second interface of the encryption engine, the key-pair associated with the subsystem for storage in the key vault;

identifying, by the encryption engine based on the key ID, a location of the key-pair associated with the subsystem in the key vault;

determining, by the encryption engine, a first tweak value based on a first sector address of the storage device, the first sector address based on the destination storage address;

encrypting, by the encryption engine, the first tweak value according to the second key of the key-pair associated with the subsystem;

encrypting, by the encryption engine, a first portion of the source data according to the first key of the key-pair associated with the subsystem and the encrypted first tweak value;

determining, by the encryption engine, a second tweak value based on a second sector address of the storage device and encrypting the second tweak value according to the second key, wherein the second tweak value is determined and encrypted during encryption of the first portion of the source data and prior to completing encryption of the first portion of the source data; and

encrypting, by the encryption engine, a second portion of the source data according to the first key and the encrypted second tweak value.

16. The method of claim 15 , further comprising obtaining, by the encryption engine, a sector address, and the key ID, wherein the encryption engine obtains a task record from a FIFO queue of the encryption engine to determine the first sector address and the key-pair.

17. The method of claim 15 , further comprising:

obtaining, by the encryption engine, a sector size for the storage device from a configuration status register associated with the storage device; and

utilizing the sector size to determine the second tweak value.

18. The method of claim 15 , further comprising:

bypassing encryption of the source data in response to determining that the source data is not received over an Advanced eXtensible Interface (AXI) write channel.

19. The method of claim 15 , further comprising:

while receiving the metadata via the first interface, concurrently transferring encrypted source data via a third interface of the plurality of interfaces, the third interface being different than the first interface.