IP Library Granted Patent US 11,601,190
Granted Patent B2
US 11,601,190 · App. 17/249,236 · Granted Mar 7, 2023

Apparatus and methods for radio frequency signal boosters

Inventors: Hongtao Zhan (Fremont, CA); Derong Lu (Shenzhen, CN)
Assignee: Cellphone-Mate, Inc.
H04B7/15557H04B1/005H04B1/38H04B1/40H04B7/155H04L5/14H04W16/26
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Quick Facts
Patent No.
US 11,601,190
App. No.
17/249,236
Granted
Mar 7, 2023
Kind
B2
Abstract

Provided herein are apparatus and methods for radio frequency signal boosters for cellular and broadcast television signals with Wi-Fi signals transmission function. Cell phone, Wi-Fi, and broadcast television signals are boosted and retransmitted over a shared antenna or over more than one antenna. In certain implementations, a multi-band signal booster is configured to provide signal path gain to at least three signal paths: a first signal path configured to receive a first time division duplexed Wi-Fi signal, a second signal path configured to receive a first frequency division duplexed mobile or cellular signal, and a second signal path configured to receive a broadcast television signal.

Claims (34)

1. An electronic system for boosting time division duplex (TDD) and frequency division duplex (FDD) signals, the electronic system comprising:

a signal booster comprising:

a diplexer configured to receive an FDD uplink signal and a TDD uplink signal from a cable, and to output the FDD uplink signal at a first terminal of the diplexer and the TDD uplink signal at a second terminal of the diplexer;

a TDD circuit including a TDD uplink signal path configured to amplify the TDD uplink signal to generate an amplified TDD uplink signal, and a TDD downlink signal path; and

an FDD circuit including a first FDD duplexer configured to receive the FDD uplink signal, a second FDD duplexer configured to output an amplified FDD uplink signal, an FDD uplink signal path having an input connected to the first FDD duplexer and an output connected to the second FDD duplexer, and an FDD downlink signal path having an input connected to the second FDD duplexer and an output connected to the first FDD duplexer.

2. The electronic system of claim 1 , further comprising:

a first antenna configured to transmit the amplified TDD uplink signal; and

a second antenna configured to transmit the amplified FDD uplink signal.

3. The electronic system of claim 1 , wherein the TDD downlink signal path is configured to amplify a TDD downlink signal to generate an amplified TDD downlink signal provided to the cable by way of the diplexer.

4. The electronic system of claim 3 , wherein the FDD downlink signal path is configured to receive an FDD downlink signal from the second FDD duplexer, and to provide an amplified FDD downlink signal to the cable by way of the first FDD duplexer and the diplexer.

5. The electronic system of claim 4 , wherein the TDD downlink signal and the TDD uplink signal form a TDD pair of a first frequency band, wherein the FDD downlink signal and the FDD uplink signal form an FDD pair of a second frequency band.

6. The electronic system of claim 4 , further comprising:

a first antenna configured to transmit the amplified TDD uplink signal and to receive the TDD downlink signal; and

a second antenna configured to transmit the amplified FDD uplink signal and to receive the FDD downlink signal.

7. The electronic system of claim 1 , wherein the signal booster further comprises at least one control knob configured to control a power level of the signal booster.

8. The electronic system of claim 1 , wherein the FDD circuit and the TDD circuit share a printed circuit board (PCB) and a power supply.

9. The electronic system of claim 1 , wherein the TDD uplink signal path, the TDD downlink signal path, the FDD uplink signal path, and the FDD downlink signal path each comprise at least one amplifier, at least one attenuator, and at least one filter.

10. The electronic system of claim 1 , further comprising a common housing for the diplexer, the TDD circuit, and the FDD circuit.

11. The electronic system of claim 1 , wherein at least one of the following are shared by both the TDD circuit and the FDD circuit: a direct current power supply, an alternating current power supply, a housing, a printed circuit board, one or more diplexers, one or more radio frequency connectors, a control circuit or processor, radio frequency shielding, internal radio frequency cabling, an amplifier, a duplexer, a multiplexer or radio frequency signal path, and a heat sink.

12. An electronic system for boosting time division duplex (TDD) and frequency division duplex (FDD) signals, the electronic system comprising:

a signal booster comprising:

a TDD circuit including a TDD downlink signal path configured to amplify a TDD downlink signal to generate an amplified TDD downlink signal, and an TDD uplink signal path;

an FDD circuit including a first FDD duplexer, a second FDD duplexer configured to receive an FDD downlink signal, an FDD uplink signal path having an input connected to the first FDD duplexer and an output connected to the second FDD duplexer, and an FDD downlink signal path having an input connected to the second FDD duplexer and an output connected to the first FDD duplexer; and

a diplexer configured to receive the amplified TDD downlink signal from the TDD circuit at a first terminal and to receive an amplified FDD downlink signal from the first FDD duplexer at a second terminal, the diplexer further configured to output the amplified TDD downlink signal and the amplified FDD downlink signal to a cable.

13. The electronic system of claim 12 , further comprising:

a first antenna configured to provide the TDD downlink signal to the TDD downlink signal path; and

a second antenna configured to provide the FDD downlink signal to the FDD duplexer.

14. The electronic system of claim 12 , wherein the TDD uplink signal path is configured to receive a TDD uplink signal from the first terminal of the diplexer, and to provide an amplified TDD uplink signal.

15. The electronic system of claim 14 , wherein the FDD uplink signal path is configured to receive an FDD uplink signal from the second terminal of the diplexer by way of the first FDD duplexer, and to provide an amplified FDD uplink signal to the second FDD duplexer.

16. The electronic system of claim 15 , wherein the TDD downlink signal and the TDD uplink signal form a TDD pair of a first frequency band, wherein the FDD downlink signal and the FDD uplink signal form an FDD pair of a second frequency band.

17. The electronic system of claim 12 , wherein the FDD circuit and the TDD circuit share a printed circuit board (PCB) and a power supply.

18. The electronic system of claim 12 , wherein the TDD uplink signal path, the TDD downlink signal path, the FDD uplink signal path, and the FDD downlink signal path each comprise at least one amplifier, at least one attenuator, and at least one filter.

19. The electronic system of claim 12 , further comprising a common housing for the diplexer, the TDD circuit, and the FDD circuit.

20. The electronic system of claim 12 , wherein at least one of the following are shared by both the TDD circuit and the FDD circuit: a direct current power supply, an alternating current power supply, a housing, a printed circuit board, one or more diplexers, one or more radio frequency connectors, a control circuit or processor, radio frequency shielding, internal radio frequency cabling, an amplifier, a duplexer, a multiplexer or radio frequency signal path, and a heat sink.

Continuity (6)
Continuation 16455399 · Jun 27, 2019
Continuation 15585080 · May 2, 2017
Continuation 15229525 · Aug 5, 2016
Continuation 14863771 · Sep 24, 2015
Provisional Application 62056344 · Sep 26, 2014
Related Publication 20210328656A1 · Oct 21, 2021