IP Library Granted Patent US 11,258,975
Granted Patent B2
US 11,258,975 · App. 17/253,990 · Granted Feb 22, 2022

Solid-state imaging device and electronic device

Inventor: Takeshi Aoki (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H04N5/37455H01L27/14612H01L27/14643H03K5/2481H04N5/378H04N5/3765H04N5/37457
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Quick Facts
Patent No.
US 11,258,975
App. No.
17/253,990
Granted
Feb 22, 2022
Kind
B2
Abstract

A solid-state imaging device that is capable of improving an imaging characteristic by enhancing a dynamic range of an ADC is provided. A solid-state imaging device that includes a pixel array including a plurality of pixels outputting a pixel signal by photoelectric conversion, and an AD conversion processing unit that performs AD conversion with respect to the pixel signal, and in which the AD conversion processing unit includes a comparator having a first amplifying unit that includes a pair of first differential pairs constituted of P-type transistors and a pair of second differential pairs constituted of N-type transistors, and a second amplifying unit that amplifies an output of the first amplifying unit, and in which a P-type transistor and an N-type transistor are connected in series is provided.

Claims (35)

1. A solid-state imaging device comprising:

a pixel array that includes a plurality of pixels outputting a pixel signal by photoelectric conversion; and

an AD conversion processing unit that performs AD conversion with respect to the pixel signal, wherein

the AD conversion processing unit includes a comparator, and the comparator includes:

a first amplifying unit that includes: a first differential pair constituted of P-type transistors; and a second differential pair constituted of N-type transistors; and

a second amplifying unit that amplifies an output of the first amplifying unit, and in which a P-type transistor and an N-type transistor are connected in series.

2. The solid-state imaging device according to claim 1 , wherein

to the first differential pair and the second differential pair, one of the pixel signal or a reference signal with which a voltage value decreases at a constant slope is selectively input.

3. The solid-state imaging device according to claim 2 , wherein

the first differential pair is constituted of a first transistor and a second transistor,

when the pixel signal is input to a gate terminal of the first transistor, the reference signal is input to a gate terminal of the second transistor, and when the reference signal is input to the gate terminal of the first transistor, the pixel signal is input to the gate terminal of the second transistor.

4. The solid-state imaging device according to claim 2 , wherein

the second differential pair is constituted of a third transistor and a fourth transistor,

when the pixel signal is input to a gate terminal of the third transistor, the reference signal is input to a gate terminal of the fourth transistor, and when the reference signal is input to the gate terminal of the third transistor, the pixel signal is input to the gate terminal of the fourth transistor.

5. The solid-state imaging device according to claim 2 , wherein

selective input to the first differential pair and the second differential pair is switched in a frame unit.

6. The solid-state imaging device according to claim 5 , wherein

the comparator is provided in each column of the pixel array, and

the selective input to the first differential pair and the second differential pair is identical in all columns.

7. The solid-state imaging device according to claim 5 , wherein

the comparator is provided in each column of the pixel array, and

the selective input to the first differential pair and the second differential pair is reversed in an adjacent column.

8. The solid-state imaging device according to claim 2 , further comprising

a timing control unit that controls selective input to the first differential pair and the second differential pair.

9. The solid-state imaging device according to claim 2 , further comprising:

a first wiring for input of the pixel signal; a second wiring for input of the reference signal; and a third wiring for output from the second amplifying unit, wherein the first wiring, the second wiring, and the third wiring are arranged in a line symmetry.

10. An electronic device, comprising:

a solid-state imaging device; and

a processing unit that processes a signal output from the solid-state imaging device, wherein

the solid-state imaging device includes:

a pixel array that includes a plurality of pixels outputting a pixel signal by photoelectric conversion; and

an AD conversion processing unit that performs AD conversion with respect to the pixel signal, wherein

the AD conversion processing unit includes a comparator, and the comparator includes:

a first amplifying unit that includes: a first differential pair constituted of P-type transistors; and a second differential pair constituted of N-type transistors; and

a second amplifying unit that amplifies an output of the first amplifying unit, and in which a P-type transistor and an N-type transistor are connected in series.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2021
From: AOKI, TAKESHI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 057077/0624 →
Priority Claims (1)
JP JP2018-122820 · Jun 28, 2018 · national
Continuity (1)
Related Publication 20210274122A1 · Sep 2, 2021