Circuit for processing a logic input

1. A circuit for processing a logic input, comprising a first comparator capable of comparing the logic input with a first reference voltage and of providing a logic output at a first output logic level if the logic input is higher than the first reference voltage and otherwise at a second output logic level different from the first output logic level, wherein the power supply of the first comparator and the first voltage reference are activated by the logic input.

2. The circuit as claimed in claim 1 , wherein the first reference voltage ranges between a minimum high input logic level and a maximum low input logic.

3. The circuit as claimed in claim 2 , wherein the first reference voltage is substantially equal to an average of the minimum high input logic level and of the maximum low input logic level.

4. The circuit as claimed in claim 1 , further comprising a switch activated by the logic input to provide the first reference voltage to the comparator.

5. A circuit for processing a logic input, comprising:

a first comparator capable of comparing the logic input with a first reference voltage and of providing a logic output at a first output logic level if the logic input is higher than the first reference voltage and otherwise at a second output logic level different from the first output logic level, and

a second comparator and a switch, the second comparator being capable of comparing the logic input with a second reference voltage and of controlling the switch so as to power the first reference voltage when the logic input is higher than the second reference voltage and otherwise so as not to power said first reference voltage,

wherein the power supply of the first comparator and the first voltage reference are activated by the logic input.

6. The circuit as claimed in claim 5 , wherein the power supply of the second comparator and the second voltage reference are activated by the logic input.

7. The circuit as claimed in claim 5 , wherein the second reference voltage is less than the first reference voltage.

8. The circuit as claimed in claim 5 , wherein the second reference voltage is equal to a fraction of a maximum low input logic level.

9. The circuit as claimed in claim 5 , wherein the second reference voltage is higher than an average noise level.

10. The circuit as claimed in claim 5 , wherein the first comparator is implemented by a first NPN type transistor, the base of which is connected to the logic input, the collector of which is connected to the logic output and the transmitter of which is connected to the first voltage reference, the second comparator is implemented by a second NPN type transistor, the base of which is connected to the logic input, the collector of which is connected to a first terminal of the switch and the transmitter of which is connected to the second voltage reference, and a second terminal of the switch is connected to the common point between the first voltage reference and the transmitter of the first transistor.

11. The circuit as claimed in claim 5 , wherein the switch is implemented by two flip-flop mounted PNP type transistors: the transmitter of the first transistor is connected to the base of the second transistor and to the transmitter of the second transistor via a resistor and the base of the first transistor is connected to the collector of the second transistor and to the transmitter of the second transistor via a resistor, the transmitter of the second transistor being connected to a biasing potential, the collector of the first transistor forming the first terminal of the switch and the collector of the second transistor forming the second terminal of the switch.

12. The circuit as claimed in claim 5 , wherein the first voltage reference is implemented by a Zener diode, the anode of which is connected to ground and the cathode of which is connected to the first comparator, and/or the second voltage reference is implemented by a Zener diode, the anode of which is connected to ground and the cathode of which is connected to the second comparator.

13. The circuit as claimed in claim 5 , wherein the second reference voltage is equal to half of a maximum low input logic level.