IP Library Granted Patent US 11,348,523
Granted Patent B2
US 11,348,523 · App. 17/271,737 · Granted May 31, 2022

Display substrate, display panel and display apparatus

Inventors: Liang Chen (Beijing, CN); Lei Wang (Beijing, CN); Li Xiao (Beijing, CN); Minghua Xuan (Beijing, CN); Dongni Liu (Beijing, CN); Hao Chen (Beijing, CN)
Assignee: BOE TECHNOLOGY GROUP CO., LTD.
G09G3/3233G09G2300/0426
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Quick Facts
Patent No.
US 11,348,523
App. No.
17/271,737
Granted
May 31, 2022
Kind
B2
Abstract

A display substrate, includes: a plurality of pixel driving circuits; a plurality of groups of light-emitting driving signal lines, wherein each driving signal line group of the plurality of groups of light-emitting driving signal lines includes a plurality of light-emitting driving signal lines; and a plurality of pixel circuit multiplexing units coupled to the plurality of pixel driving circuits, respectively, wherein each pixel circuit multiplexing unit includes N light-emitting units coupled to one of the plurality of pixel driving circuits and a group of light-emitting driving signal line.

Claims (44)

1. A display substrate, comprising:

a plurality of pixel driving circuits;

a plurality of groups of light-emitting driving signal lines, wherein each driving signal line group of the plurality of groups of light-emitting driving signal lines comprises a plurality of light-emitting driving signal lines; and

a plurality of pixel circuit multiplexing units coupled to the plurality of pixel driving circuits, respectively, wherein the plurality of pixel circuit multiplexing units are arranged in a first array of D×E, and D and E are integers greater than 1,

wherein each pixel circuit multiplexing unit of the plurality of pixel circuit multiplexing unit comprises N light-emitting units arranged in a second array of K×H, wherein K, H and N are integers greater than 1, and the N light-emitting units are coupled to one of the plurality of groups of light-emitting driving signal lines; and

wherein each light-emitting unit of the N light-emitting units is configured to receive a driving signal from a pixel driving circuit coupled to the each light-emitting unit, under control of a light-emitting driving signal from a light-emitting driving signal line coupled to the each light-emitting unit, so that all light-emitting units located in a same row do not emit light at the same time, all light-emitting units located in a same column emit light at different times, and the N light-emitting units in a same pixel circuit multiplexing unit emit light in sequence during one frame period,

wherein the ach light emitting unit of the N light-emitting units comprises:

a driving transistor having a gate coupled to one of the plurality of light-emitting driving signal lines, and a first electrode coupled to one of the plurality of pixel driving circuits; and

a light-emitting device having an anode coupled to a second electrode of the driving transistor, and a cathode coupled to a reference signal line,

wherein the gate of the driving transistor is arranged in a gate layer of the display substrate, the first electrode of the driving transistor and the second electrode of the driving transistor are arranged in a source or a drain layer of the display substrate, and the anode of the light-emitting device is arranged in an anode layer of the display substrate; and

wherein the anode of the light-emitting device comprises a protrusion in the anode layer, and wherein the protrusion extends to one of the plurality of light-emitting driving signal lines, and s coupled the second electrode of the driving transistor in the source/drain layer through a via hole,

wherein a length of a protrusion of an anode of a light-emitting device located in a row and a column is different from a length of a protrusion of an anode of a light-emitting device located in the same row and an adjacent column.

2. The display substrate according to claim 1 , wherein the plurality of pixel circuit multiplexing units are coupled to the plurality of pixel driving circuits in one-to-one correspondence, and the N light-emitting units in the each pixel circuit multiplexing unit are coupled to a same pixel driving circuit in the plurality of pixel driving circuits.

3. The display substrate according to claim 2 , wherein the each driving signal line group comprises N light-emitting driving signal lines; and

wherein the N light-emitting driving signal lines extend in a first direction and are arranged in a second direction, and the first direction is a row direction of the first array and the second array, and the second direction is a column direction of the first array and the second array; and

wherein pixel circuit multiplexing units located in a same row of the first array are coupled to a group of light-emitting driving signal lines.

4. The display substrate according to claim 3 , wherein N=2, and the each pixel circuit multiplexing unit comprises a first light-emitting unit and a second light-emitting unit arranged in a column, and the N light-emitting driving signal lines comprise a first light-emitting driving signal line and a second light-emitting driving signal line; and

wherein a first light-emitting unit in a pixel circuit multiplexing unit located in an i th row and a j th column of the first array and a second light-emitting unit in a pixel circuit multiplexing unit located in the i th row and a (j+1) th column of the first array are coupled to the first light-emitting driving signal line, wherein i and j are integers, and 1≤i≤D, 1≤j≤E; and

a second light-emitting unit in the pixel circuit multiplexing unit located in the i th row and the j th column of the first array and a first light-emitting unit in pixel circuit multiplexing unit located in the i th row and the (j+1) th column of the first array are coupled to the second light-emitting driving signal line.

5. The display substrate according to claim 4 , wherein the first light-emitting driving signal line and the second light-emitting driving signal line are in a linear shape and extend in the first direction; and

wherein the first light-emitting unit in the pixel circuit multiplexing unit located in an i th row and a j th column of the first array and the second light-emitting unit in the pixel circuit multiplexing unit located in the i th row and a (j+1) th column of the first array are coupled to the first light-emitting driving signal line through a via hole, wherein i and j are integers, and 1≤i≤D, 1≤j≤E; and

the second light-emitting unit in the pixel circuit multiplexing unit located in the i th row and the j th column of the first array and the first light-emitting unit in the pixel circuit multiplexing unit located in the i th row and the (j+1) th column of the first array are coupled to the second light-emitting driving signal line through a via hole.

6. The display substrate according to claim 4 , wherein,

the first light-emitting driving signal line is in a first zigzag shape and extends in the first direction, so as to couple to the first light-emitting unit in the pixel circuit multiplexing unit located in the i th row and the j th column and the second light-emitting unit in the pixel circuit multiplexing unit located in the i th row and the (j+1) th column; and

the second light-emitting driving signal line is in a second zigzag shape and extends in the first direction, so as to couple to the second light-emitting unit in the pixel circuit multiplexing unit located in the i th row and the j th column and the first light-emitting unit in the pixel circuit multiplexing unit located in the i th row and the (j+1) th column.

7. The display substrate according to claim 3 , wherein N is an even number greater than 2, and the N light-emitting driving signal lines in the each driving signal line group are arranged in the second direction in an order from the first light-emitting driving signal line to the N th light-emitting driving signal line; and

wherein a light-emitting unit located in a k th row and an h th column of the second array is coupled to an n th light-emitting driving signal line in the N light-emitting driving signal lines, wherein k, h and N are integers greater than 1, 1≤k≤K, 1≤h≤H, and n=(k−1)H+h.

8. The display substrate according to claim 2 , further comprising:

a plurality of groups of light-emitting control lines, wherein the each pixel circuit multiplexing unit is coupled to a group of light-emitting control lines, and each control line group comprises M light-emitting control lines; and

wherein the N light-emitting units in the pixel circuit multiplexing unit are divided into M groups of light-emitting units, and the pixel circuit multiplexing unit further comprises M switching circuits; and

wherein an m th switching circuit is coupled to an m th light-emitting control line, an m th group of light-emitting units and a pixel driving circuit, and the m th switching circuit is configured to provide a driving current generated by the pixel driving circuit to the m th group of light-emitting units under control of an m th light-emitting control signal from the m th light-emitting control line, wherein M is an integer greater than 1, m is an integer, and 1≤m≤M.

9. The display substrate according to claim 8 , wherein,

the plurality of light-emitting driving signal lines extend in the second direction and are arranged in the first direction, and the M light-emitting control lines extend in the first direction and are arranged in the second direction; and

wherein a pixel circuit multiplexing unit located in a same column of the first array is coupled to a group of light-emitting driving signal lines, and a pixel circuit multiplexing unit located in a same row of the first array is coupled to a group of light-emitting control lines.

10. The display substrate according to claim 9 , wherein M=2, the M light-emitting control lines comprise a first light-emitting control line and a second light-emitting control line; and

wherein the M groups of the light-emitting units comprises a first group of light-emitting units and a second group of the light-emitting units, and the M switching circuits comprise a first switching circuit and a second switching circuit; and

wherein the first switching circuit comprises a first transistor, a gate of the first transistor is coupled to the first light-emitting control line, a first electrode of the first transistor is coupled to the pixel driving circuit, and a second electrode of the first transistor is coupled to the first group of the light-emitting units; and

the second switching circuit comprises a second transistor, a gate of the second transistor is coupled to the second light-emitting control line, a first electrode of the second transistor is coupled to the pixel driving circuit, and a second electrode of the second transistor is coupled to the second group of the light-emitting units.

11. The display substrate according to claim 8 , wherein M=2, the M light-emitting control lines comprise a first light-emitting control line and a second light-emitting control line; and

wherein the M groups of the light-emitting units comprises a first group of light-emitting units and a second group of the light-emitting units, and the M switching circuits comprise a first switching circuit and a second switching circuit; and

wherein the first switching circuit comprises a first transistor, a gate of the first transistor is coupled to the first light-emitting control line, a first electrode of the first transistor is coupled to the pixel driving circuit, and a second electrode of the first transistor is coupled to the first group of the light-emitting units; and

the second switching circuit comprises a second transistor, a gate of the second transistor is coupled to the second light-emitting control line, a first electrode of the second transistor is coupled to the pixel driving circuit, and a second electrode of the second transistor is coupled to the second group of the light-emitting units.

12. A display panel, comprising a display substrate according to claim 1 .

13. A display apparatus, comprising the display panel according to claim 12 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2023
From: BOE TECHNOLOGY GROUP CO., LTD.
To: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
Reel/Frame 064397/0480 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2021
From: CHEN, LIANG; WANG, LEI; XIAO, LI; XUAN, MINGHUA; LIU, DONGNI; CHEN, HAO
To: BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 055432/0350 →
Priority Claims (1)
CN 201910689209.6 · Jul 29, 2019 · national
Continuity (1)
Related Publication 20210319748A1 · Oct 14, 2021
Cited By (3)
US 12,232,384 US 12,261,193 US 12,324,327