Time delay integration structure for complementary metal-oxide semiconductor imaging sensor

1. A system for time delay integration in Complementary Metal Oxide Semiconductor (CMOS) imaging sensors, the system comprising:

a two dimensional parallel charge transfer structure comprising at least one column of CMOS photodiodes;

each said photodiode in the column being connected to the next diode by a two phase transfer gate, each said transfer gate having a barrier and a well configured such that a flow of charge in the column is unidirectional.

2. The system of claim 1 wherein each said well is configured to hold the full well capacity of a pixel.

3. The system of claim 1 further comprising a microlens disposed so as to direct photons between said transfer gates into said photodiodes.

4. The system of claim 1 further comprising at least one color filter.

5. The system of claim 1 wherein said system comprises a plurality of the columns of CMOS photodiodes in an array.

6. The system of claim 5 wherein said system comprises a plurality of said arrays.

7. A method for manufacturing a time delay integrated Complementary Metal Oxide Semiconductor (CMOS) imaging sensor, said method comprising:

starting with a wafer substrate;

isolating at least one pixel;

doping at least a first region of said substrate for at least one transfer well;

doping at least a second region of said substrate to form at least one transfer barrier;

forming a transfer gate from said at least one transfer barrier;

doping at least a third region of said substrate to form a photodiode barrier;

doping at least a fourth region of said substrate to form a photodiode well;

forming gate sidewalls in said substrate;

applying a photodiode pinning layer to said substrate;

forming at least one connection on said substrate, said connection being selected from the group of connections consisting of contacts, metal vias, and interconnects; and

producing of at least one chip from said substrate.

8. The method of claim 7 wherein said isolating said at least one pixel comprises forming shallow trenches between columns of said pixels.

9. The method of claim 8 wherein said step of forming shallow trenches between said columns of said pixels is by etching said shallow trenches between said columns of said pixels.

10. The method of claim 7 wherein said isolating at least one pixel comprises doping said wafer substrate in a pattern so as to isolate said pixel.

11. The method of claim 7 further comprising:

doping at least a fifth region of said substrate as a Field Effect Transistor (FET) threshold shift region;

forming a FET from said FET threshold shift region; and

doping said fifth region of said substrate to form at least one FET source and at least one FET drain.

12. The method of claim 7 , further comprising forming a sensor from said chip 11 The method of claim 7 further comprising disposing at least one microlens proximate to said at least one pixel, such that light passing through said microlens is directed toward a photodiode comprising said photodiode barrier and photodiode well.