IP Library Granted Patent US 11,882,710
Granted Patent B2
US 11,882,710 · App. 17/275,547 · Granted Jan 23, 2024

Thin-film transistor comprising organic semiconductor materials

Inventors: Antonio Facchetti (Skokie, IL); Yu Xia (Skokie, IL); Zhihua Chen (Skokie, IL); Timothy Chiu (Skokieil, IL); Shaofeng Lu (Skokie, IL)
Assignee: Flexterra, Inc.
H10K10/484H10K10/471H10K85/621
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,882,710
App. No.
17/275,547
Granted
Jan 23, 2024
Kind
B2
Abstract

This invention relates to a thin-film transistor including, a dielectric layer having a first side and an opposed second side; a source electrode, a drain electrode separated from the source electrode, and a semiconductor component disposed between and in contact with the source electrode and the drain electrode, the source electrode, the drain electrode and the semiconductor component being disposed adjacent the first side of the dielectric layer; and a gate electrode disposed adjacent the second side of the dielectric layer opposite the semiconductor component; wherein the semiconductor component comprises one or more n-type organic semiconductor materials based on arene-bis(dicarboximide)s, and wherein the thin-film transistor has a channel length, measured as the shortest path from the source electrode to the drain electrode, of no more than 20 μm.

Claims (37)

1. A thin-film transistor comprising

a dielectric layer having a first side and a second side opposed to said first side;

a source electrode, a drain electrode separated from the source electrode, and a semiconductor component disposed between and in contact with said source electrode and said drain electrode, said source electrode, said drain electrode and said semiconductor component being disposed adjacent the first side of said dielectric layer; and

a gate electrode disposed adjacent the said second side of the dielectric layer opposite said semiconductor component;

wherein the semiconductor component comprises one or more of the following pairs of compounds:

in a molar ratio of compounds 1A to 1B in the range of 3:1 to 50:1,

in a molar ratio of compounds 2A to 2B in the range of 3:1 to 50:1, and

in a molar ratio of compounds 3A to 3B in the range of 3:1 to 50:1;

wherein said thin-film transistor has a channel length in the range of 3-20 μm, said channel length being measured as the shortest path from the source electrode to the drain electrode.

2. The transistor of claim 1 , wherein the semiconductor component

in a molar ratio of compounds 1A to 1B in the range of 3:1 to 50:1.

3. The transistor of claim 1 , wherein the semiconductor component comprises

in a molar ratio of compounds 2A to 2B in the range of 3:1 to 50:1.

4. The transistor of claim 1 , wherein the semiconductor component

in a molar ratio of compounds 3A to 3B in the range of 3:1 to 50:1.

5. The transistor of claim 1 , wherein said semiconductor component is formed from at least 75 wt. % of the one or more pairs of compounds.

6. The transistor of claim 1 , wherein said channel length is in the range of 3-18 μm.

7. The transistor of claim 1 , wherein said channel length is no more than 10 μm.

8. The transistor of claim 1 , wherein said semiconductor component has a thickness within the range of 10 nm to 100 nm.

9. The transistor of claim 1 , wherein said channel has a width perpendicular to the semiconductor component thickness and to the channel length, said width being within the range of 0.01 mm to 4 mm.

10. The transistor of claim 1 , wherein each of said source electrode, drain electrode, and gate electrode independently comprises a gold layer, a silver layer, a copper layer, or a molybdenum layer.

11. The transistor of claim 1 , wherein one or more of said source electrode, drain electrode, and gate electrode independently comprises a silver layer.

12. The transistor of claim 1 , further comprising a substrate supporting said semiconductor component, said dielectric layer, said source electrode, said drain electrode and said gate electrode.

13. The transistor of claim 1 , wherein each of said source electrode, drain electrode, and gate electrode independently has a thickness in the direction of the semiconductor component thickness within the range of 30 nm to 500 nm.

14. The transistor of claim 1 , wherein said dielectric layer has a dielectric constant in the range of 2.5-25.

15. The transistor of claim 1 , having a carrier mobility that is at least 50% of a carrier mobility of an otherwise identical transistor having a channel length of 50 μm.

16. The transistor of claim 1 , wherein

said semiconductor component has a thickness within the range of 10 nm to 100 nm; and

said channel has a width perpendicular to the semiconductor component thickness and to the channel length, said width being within the range of 0.01 mm to 4 mm.

17. The transistor of claim 16 ,

wherein each of said source electrode, drain electrode, and gate electrode independently comprises a gold layer, a silver layer, a copper layer, or a molybdenum layer; and

wherein each of said source electrode, drain electrode, and gate electrode independently has a thickness in the direction of the semiconductor component thickness within the range of 30 nm to 500 nm.

18. The transistor of claim 17 wherein one or more of said source electrode, drain electrode, and gate electrode independently comprises a silver layer.

19. The transistor of claim 1 , wherein said channel length is in the range of 5-15 μm.

20. The transistor of claim 1 , having a carrier mobility that is at least 55% of a carrier mobility of an otherwise identical transistor having a channel length of 50 μm.

21. The transistor of claim 12 , wherein the substrate is a polyethylene naphthalate substrate.

22. The transistor of claim 1 , wherein each of the ratios is in a range of 3.5:1 to 25:1.

Assignments (4)
ASSET PURCHASE AGREEMENT Recorded Dec 13, 2025
From: FLEXTERRA, INC.; FLEXTERRA TAIWAN CORPORATION LIMITED
To: USINVEST, LLC
Reel/Frame 073948/0751 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 5, 2025
From: FLEXTERRA, INC.
To: USINVEST LLC
Reel/Frame 073464/0376 →
SECURITY INTEREST Recorded Feb 10, 2022
From: FLEXTERRA, INC.
To: SAES GETTERS INTERNATIONAL LUXEMBOURG S.A., IN ITS CAPACITY AS COLLATERAL AGENT
Reel/Frame 059008/0757 →
NUNC PRO TUNC ASSIGNMENT Recorded Mar 11, 2021
From: FACCHETTI, ANTONIO; XIA, YU; CHEN, ZHIHUA; CHIU, TIMOTHY; LU, SHAOFENG
To: FLEXTERRA, INC.
Reel/Frame 055567/0244 →
Priority Claims (1)
EP 18210830 · Dec 6, 2018 · regional
Continuity (2)
Provisional Application 62769756 · Nov 20, 2018
Related Publication 20210257568A1 · Aug 19, 2021