IP Library Granted Patent US 11,619,838
Granted Patent B2
US 11,619,838 · App. 17/302,632 · Granted Apr 4, 2023

Optical modulator using monocrystalline and polycrystalline silicon

Inventors: Xunyuan Zhang (Mechanicsburg, PA); Vipulkumar K. Patel (Breinigsville, PA); Prakash B. Gothoskar (Allentown, PA); Ming Gai Stanley Lo (Breinigsville, PA)
Assignee: Cisco Technology, Inc.
G02F1/025G02F2202/104G02F2202/105
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Quick Facts
Patent No.
US 11,619,838
App. No.
17/302,632
Granted
Apr 4, 2023
Kind
B2
Abstract

Embodiments provide for an optical modulator, comprising: a lower guide, comprising: a lower hub, made of monocrystalline silicon; and a lower ridge, made of monocrystalline silicon that extends in a first direction from the lower hub; an upper guide, including: an upper hub; and an upper ridge, made of monocrystalline silicon that extends in a second direction, opposite of the first direction, from the upper hub and is aligned with the lower ridge; and a gate oxide layer separating the lower ridge from the upper ridge and defining a waveguide region with the lower guide and the upper guide.

Claims (45)

1. A method of forming an optical modulator, comprising:

patterning a base component to impart:

a lower waveguide that is separated from a substrate of the base component by a first layer of an insulator;

an upper ridge for an upper waveguide that is located above the lower waveguide and is separated from the lower waveguide by a predefined height;

depositing a gate oxide layer on the lower waveguide;

depositing a second layer of the insulator on the gate oxide layer;

etching the second layer of the insulator to define a cavity of a predefined shape; and

forming polycrystalline silicon wings for the upper waveguide in the cavity.

2. The method of claim 1 , further comprising:

forming a first set of contacts through the second layer of the insulator to form a first electrical connection through the lower waveguide; and

forming a second set of contacts through the second layer of the insulator to form a second electrical connection through the upper waveguide.

3. The method of claim 1 , wherein the base component comprises:

the substrate;

the first layer of the insulator, formed on the substrate;

a Silicon-On-Insulator (SOI) layer, formed on the first layer of the insulator and doped to exhibit a first type of conductivity, wherein patterning the base component imparts the lower waveguide in the SOI layer;

a spacing layer, formed on the SOI layer; and

a second silicon layer, formed on the spacing layer and doped to exhibit a different type of conductivity than the SOI layer, wherein patterning the base component imparts the upper ridge in the second silicon layer.

4. The method of claim 3 , further comprising:

prior to patterning a base component, applying a cap layer to the second silicon layer; and

wherein patterning the base component further imparts a cap, made from the cap layer, extending upward from the upper ridge.

5. The method of claim 3 , further comprising:

patterning the base component to impart an optical source aligned along a light path with the upper waveguide and the lower waveguide.

6. The method of claim 3 , wherein the spacing layer is of the predefined height and made from a Silicon Germanium material; and

wherein patterning the base component further comprises:

applying an anchor material;

removing the spacing layer while the anchor material suspends the upper ridge above the lower waveguide;

wherein depositing the gate oxide layer on the lower waveguide fills a space previously occupied by the spacing layer between the upper ridge and the lower waveguide; and

in response to depositing the gate oxide layer, removing the anchor material.

7. The method of claim 6 , further comprising:

prior to removing the anchor material, applying an additional layer of the insulator on the gate oxide layer.

8. The method of claim 1 , wherein a portion of the upper ridge that extends upward for a first height into the cavity defines an upper hub, and wherein forming the polycrystalline silicon wings further comprises:

depositing a polycrystalline layer in the cavity;

etching a first wing of a first length and the first height into the polycrystalline layer on a first side of the upper hub;

etching a second wing of the first length and the first height into the polycrystalline layer on a second side of the upper hub;

etching a first interface of a second height greater than the first height into the polycrystalline layer on the first side of the first wing; and

etching a second interface of the second height into the polycrystalline layer on the second side of the second wing.

9. The method of claim 1 , wherein forming the polycrystalline silicon wings further comprises:

forming a single crystal silicon hub of a given height on the upper ridge;

forming, on a first side of the single crystal silicon hub, a first wing of the polycrystalline silicon wings at the given height;

forming on a second side of the single crystal silicon hub, a second wing of the polycrystalline silicon wings at the given height;

patterning the polycrystalline silicon wings to a given length; and

applying an additional layer of the insulator on the polycrystalline silicon wings and the single crystal silicon hub.

10. The method of claim 1 , wherein forming the polycrystalline silicon wings for the upper waveguide in the cavity aligns the polycrystalline silicon wings with a hub of the upper ridge.

11. The method of claim 1 , further comprising:

prior to forming the polycrystalline silicon wings, growing a hub as a single Silicon crystal on the upper ridge, wherein the polycrystalline silicon wings are aligned with the hub.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2021
From: ZHANG, XUNYUAN; PATEL, VIPULKUMAR K.; GOTHOSKAR, PRAKASH B.; LO, MING GAI STANLEY
To: CISCO TECHNOLOGY, INC.
Reel/Frame 056176/0098 →
Continuity (2)
Division 16356982 · Mar 18, 2019
Related Publication 20210263351A1 · Aug 26, 2021