Semiconductor device structure with multiple liners and method for forming the same
The present disclosure provides a semiconductor device structure with a silicon-on-insulator (SOI) region and a method for forming the semiconductor device structure. The semiconductor device structure also includes a well region disposed in a semiconductor substrate, a first shallow trench isolation (STI) structure extending into the well region. The first STI structure comprises a first liner contacting the well region; a second liner covering the first liner and contacting the pad oxide layer and the pad nitride layer; a third liner covering the second liner, wherein the first liner, the second liner and the third liner are made of different materials; and a first trench filling layer disposed over the third liner and separated from the second liner by the third liner.
1. A semiconductor device structure, comprising:
a well region disposed in a semiconductor substrate, wherein a region of the semiconductor substrate under the well region has a first conductivity type, and the well region has a second conductivity type opposite to the first conductivity type;
a pad oxide layer disposed over the semiconductor substrate;
a pad nitride layer disposed over the pad oxide layer;
a first shallow trench isolation (STI) structure penetrating through the pad oxide layer and the pad nitride layer and extending into the well region, wherein the first STI structure comprises:
a first liner contacting the well region;
a second liner covering the first liner and contacting the pad oxide layer and the pad nitride layer;
a third liner covering the second liner, wherein the first liner, the second liner and the third liner are made of different materials; and
a first trench filling layer disposed over the third liner and separated from the second liner by the third liner;
wherein the second liner includes an upper portion deposited between the pad oxide layer and the third liner and between the pad nitride layer and the third liner, and a lower portion deposited between the first liner and the third liner, a thickness of the upper portion of the second liner is greater than a thickness of the lower portion of the second liner.
2. The semiconductor device structure of claim 1 , wherein the first liner completely separates the second liner from the well region.
3. The semiconductor device structure of claim 1 , wherein a topmost surface of the second liner is higher than a topmost surface of the first liner.
4. The semiconductor device structure of claim 1 , wherein the first liner is made of silicon oxide, the second liner is made of nitride, and the third liner is made of silicon oxynitride, and
wherein a first etching selectivity exists between the second liner and the first trench filling layer, and a second etching selectivity exists between the third liner and the first trench filling layer.
5. The semiconductor device structure of claim 1 , further comprising:
a second shallow trench isolation (STI) structure penetrating through the pad oxide layer and the pad nitride layer and extending into the well region, wherein the second STI structure comprises:
a second trench filling layer; and
a fourth liner separating the second trench filling layer from the pad oxide layer, the pad nitride layer and the well region.
6. The semiconductor device structure of claim 5 , wherein the first conductivity type is n-type, and the second conductivity type is p-type, and wherein a bottom surface of the first STI structure and a bottom surface of the second STI structure are higher than a bottom surface of the well region.
7. The semiconductor device structure of claim 5 , wherein the first STI structure is disposed in an array area, and the second STI structure is disposed in a peripheral circuit area.