Automation for monolithic 3D devices
A method of designing a 3D Integrated Circuit, the method comprising: performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory; then performing a first placement of said logic strata using a 2D placer executed by a computer, wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices, wherein said 3D Integrated Circuit comprises through silicon vias for connection between said logic strata and said memory strata; and performing a second placement of said memory strata based on said first placement, wherein said memory comprises a first memory array, wherein said logic comprises a first logic circuit controlling said first memory array, wherein said first placement comprises placement of said first logic circuit, and wherein said second placement comprises placement of said first memory array based on said placement of said first logic circuit.
1. A method of designing a 3D Integrated Circuit, the method comprising:
performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory; then
performing a first placement of said logic strata using a 2D placer executed by a computer,
wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices,
wherein said 3D Integrated Circuit comprises through silicon vias for connection between said logic strata and said memory strata; and
performing a second placement of said memory strata based on said first placement,
wherein said memory comprises a first memory array,
wherein said logic comprises a first logic circuit controlling said first memory array,
wherein said first placement comprises placement of said first logic circuit, and
wherein said second placement comprises placement of said first memory array based on said placement of said first logic circuit.
2. The method according to claim 1 ,
wherein said logic strata comprises first routing layers,
wherein said memory strata comprises second routing layers, and said method further comprising:
performing routing for said first routing layers and said second routing layers.
3. The method according to claim 1 ,
wherein said first logic circuit comprises at least one decoder or at least one decoder representation.
4. The method according to claim 1 ,
wherein said memory comprises a second memory array,
wherein said first memory array comprises a first decoder,
wherein said second memory array comprises a second memory decoder, and
wherein said 2D placer is set so said second decoder is not placed within a rectangle at least partially defined by placement of said first decoder.
5. The method according to claim 1 ,
wherein said first logic circuit comprises at least one decoder representation,
wherein said decoder representation is placed on said logic strata,
wherein an actual memory decoder and associated bit cells are placed on said memory strata, and
wherein placement of said actual memory decoder and associated bit cells is based on said decoder representation placement.
6. The method according to claim 1 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit.
7. A method of designing a 3D Integrated Circuit, the method comprising:
performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory; then
performing a first placement of said logic strata using a 2D placer executed by a computer,
wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; and
performing a second placement of said memory strata based on said first placement,
wherein said logic comprises at least one decoder representation for said memory, and
wherein said memory comprises at least a first memory and a second memory,
wherein said first memory comprises a first memory decoder representation and said second memory comprises a second memory decoder representation,
wherein said 2D placer is set so said second memory decoder representation is not placed within a rectangle defined by placement of said first memory decoder representation.
8. The method according to claim 7 ,
wherein a majority of said memory strata comprises memory bit cells.
9. The method according to claim 7 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit.
10. The method according to claim 7 ,
wherein performing a second placement comprises use of said 2D placer.
11. The method according to claim 7 ,
wherein said at least one decoder representation has a virtual size with a width of contacts for through silicon vias, and
wherein said performing a first placement comprises placement of said contacts.
12. The method according to claim 7 ,
wherein said logic strata comprises first routing layers,
wherein said memory strata comprises second routing layers, and
said method further comprising:
performing routing for said first routing layers and said second routing layers.
13. The method according to claim 7 , further comprising:
performing a synthesis step utilizing at least two libraries.
14. A method of designing a 3D Integrated Circuit, the method comprising:
performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory; then
performing a first placement of said logic strata using a 2D placer executed by a computer,
wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices; and
performing a second placement of said memory strata based on said first placement,
wherein said partitioning comprises a step of assigning at least one logic block to said memory strata for improved balancing of said logic strata area and said memory strata area.
15. The method according to claim 14 ,
wherein results of said method of designing a 3D Integrated Circuit are utilized to form an integrated circuit.
16. The method according to claim 14 ,
wherein said logic strata comprises first routing layers,
wherein said memory strata comprises second routing layers, and said method further comprising:
performing routing for said first routing layers and said second routing layers.
17. The method according to claim 14 ,
wherein said memory comprises at least a first memory and a second memory,
wherein said first memory comprises a first memory decoder and said second memory comprises a second memory decoder, and
wherein said 2D placer is set so said second memory decoder is not placed within a rectangle defined by placement of said first memory decoder.
18. The method according to claim 14 ,
wherein said performing placement comprises placement of said at least one decoder for at least a portion of said memory, and
wherein the placement of said at least a portion of said memory is defined by the placement of said at least one decoder.
19. The method according to claim 14 ,
wherein said at least one decoder representation has a virtual size with width of contacts for through silicon vias, and
wherein said performing a first placement comprises using said decoder representation instead of an actual memory decoder.
20. The method according to claim 14 , further comprising:
performing a synthesis step utilizing at least two libraries.