Memory access handling for peripheral component interconnect devices

1. A method comprising:

receiving, by a host computing system, a memory access request initiated by a peripheral component interconnect (PCI) device, wherein the memory access request comprises a memory address and a first address translation flag indicative of whether the memory access request is a translated memory access request or an untranslated memory access request;

responsive to determining that the first address translation flag is set to a first value indicating that the memory access request is a translated memory access request, causing a host system input/output memory management unit (IOMMU) to pass-through the memory access request to host memory;

receiving an interrupt request initiated by the PCI device, wherein the interrupt request comprises the memory address and a second address translation flag;

responsive to determining that the second address translation flag is set to a second value, causing the host system IOMMU to translate the memory address specified by the interrupt request; and

sending the translated interrupt request to a virtual central processing unit (vCPU) of a virtual machine.

2. The method of claim 1 , further comprising

configuring, by the host computing system, the PCI device to translate memory access requests using an on-device IOMMU.

3. The method of claim 1 , further comprising:

configuring, by the host computing system, the PCI device to append an address translation flag set to the first value to each memory access request translated by a on-device IOMMU.

4. The method of claim 1 , further comprising:

receiving, by the host computing system, a further memory access request initiated by the PCI device, wherein the memory access request comprises a memory address; and

responsive to determining that the memory address is within a specific address range, causing the host system IOMMU to pass-through the memory access request.

5. A system, comprising:

a memory;

a processing device operatively coupled to the memory, the processing device configured to:

receive a memory access request initiated by a peripheral component interconnect (PCI) device, wherein the memory access request comprises a memory address and a first address translation flag indicative of whether the memory access request is a translated memory access request or an untranslated memory access request;

responsive to determining that the first address translation flag is set to a first value indicating that the memory access request is a translated memory access request, causing a host system input/output memory management unit (IOMMU) to pass-through the memory access request to host memory;

receive an interrupt request initiated by the PCI device, wherein the interrupt request comprises the memory address and a second address translation flag;

responsive to determining that the second address translation flag is set to a second value, cause the host system IOMMU to translate the memory address specified by the interrupt request; and

send the translated interrupt request to a virtual central processing unit (vCPU) of a virtual machine.

6. The system of claim 5 , wherein the processing device is further configured to:

configure the PCI device to translate memory access requests using an on-device IOMMU.

7. The system of claim 5 , wherein the processing device is further configured to:

configure the PCI device to append an address translation flag set to the first value to each memory access request translated by a on-device IOMMU.

8. The system of claim 5 , wherein the processing device is further configured to:

receive a further memory access request initiated by the PCI device, wherein the memory access request comprises a memory address; and

responsive to determining that the memory address is within a specific address range, cause the host system IOMMU to pass-through the memory access request.

9. A non-transitory machine-readable storage medium storing executable instructions that, when executed by a processing device, cause the processing device to:

receive a memory access request initiated by a peripheral component interconnect (PCI) device, wherein the memory access request comprises a memory address and a first address translation flag indicative of whether the memory access request is a translated memory access request or an untranslated memory access request;

responsive to determining that the first address translation flag is set to a first value indicating that the memory access request is a translated memory access request, causing a host system input/output memory management unit (IOMMU) to pass-through the memory access request to host memory;

receive an interrupt request initiated by the PCI device, wherein the interrupt request comprises the memory address and a second address translation flag;

responsive to determining that the second address translation flag is set to a second value, cause the host system IOMMU to translate the memory address specified by the interrupt request; and

send the translated interrupt request to a virtual central processing unit (vCPU) of a virtual machine.

10. The non-transitory machine-readable storage medium of claim 9 , further comprising executable instructions that, when executed by the processing device, cause the processing device to:

configure the PCI device to translate memory access requests using an on-device IOMMU; and

configure the PCI device to append an address translation flag set to the first value to each memory access request translated by the on-device IOMMU.

11. The non-transitory machine-readable storage medium of claim 9 , wherein the processing device is further configured to:

receive a further memory access request initiated by the PCI device, wherein the memory access request comprises a memory address; and

responsive to determining that the memory address is within a specific address range, cause the host system IOMMU to pass-through the memory access request.