Cubic low-density parity-check code encoder

1. A method for creating a low-density parity-check code (LDPC) using an encoder and a decoder, the method comprising:

positioning, using the encoder, coded bits comprising information bits, 0 or more constant bits, and check bits in a three-dimensional matrix having ranks, columns, and rows; and

calculating, using the encoder, the check bits such that a modulo-2 sum across the ranks of all combinations of columns and rows, and across the columns of all combinations of ranks and rows, and across the rows of all combinations of ranks and columns is 0; and

using the decoder, and based at least on the LDPC, performing error correction in a communication system.

2. The method of claim 1 , wherein the three-dimensional matrix includes basic bits arranged in Nx−1 ranks, Ny−1 columns, and Nz−1 rows of a three-dimensional matrix;

wherein an Nx rank includes check bits, each of the check bits in the Nx rank being the sum modulo 2 across ranks 1 to Nx−1 for each combination of column y, 1≤y≤Ny−1, and row z, 1≤z≤Nz−1;

wherein an Ny column includes check bits, each of the check bits in the Ny column being the sum modulo 2 across columns 1 to Ny−1 for each combination of rank x, 1≤x≤Nx, and row z, 1≤z≤Nz−1; and

wherein an Nz row includes check bits, each of the check bits in the Nz row being the sum modulo 2 across rows 1 to Nz−1 for each combination of rank x, 1≤x≤Nx, and column y, 1≤y≤Ny.

3. The method of claim 2 , wherein the basic bits comprise the information bits, 0 or more constant bits, additional check bits, or combinations thereof.

4. The method of claim 1 , wherein values of the check bits are further calculated such that the modulo-2 sum across one or more paths through the matrix is 0, a length of each path being equal to a minimum of the number of ranks, columns, and rows; and

each bit of the path not having a same rank as any other bit of the path;

each bit of the path not having a same column as any other bit of the path; and

each bit of the path not having a same row as any other bit of the path.

5. The method of claim 4 , wherein at least one position defined by a selected rank and a selected row and a selected column is not associated with an information bit, and wherein the method further comprises calculating a check bit for the at least one position using bits located at a diagonal pattern of ranks, columns, and rows.

6. The method of claim 5 , wherein multiple positions defined by certain rank and certain row and column combinations are not associated with any information bit but are associated with check bits.

7. The method of claim 6 , further comprising calculating multiple check bits of the multiple positions using bits at respective diagonal patterns of ranks, columns, and rows.

8. A method for creating a low-density parity-check code (LDPC) using an encoder and a decoder by:

positioning, using the encoder, coded bits comprising information bits, 0 or more constant bits, and check bits in a four-dimensional matrix having files, ranks, columns, and rows; and

calculating, using the encoder, the check bits such that a modulo-2 sum across the files of all combinations of ranks, columns, and rows, across the ranks of all combinations of files, columns, and rows, across the columns of all combinations of files, ranks, and rows, and across the rows of all combinations of files, ranks, and columns is 0; and

using the decoder, and based at least on the LDPC, performing error correction in a communication system.

9. The method of claim 8 , wherein the four-dimensional matrix includes basic bits arranged in Nw−1 files, Nx−1 ranks, Ny−1 columns, and Nz−1 rows of a four-dimensional matrix;

wherein an Nw file includes check bits, each of the check bits in the Nw file being the sum modulo 2 across files 1 to Nw−1 for each combination of rank x, 1≤x≤Nx−1, column y, 1≤y≤Ny−1, and row z, 1≤z≤Nz−1;

wherein an Nx rank includes check bits, each of the check bits in the Nx rank being the sum modulo 2 across ranks 1 To Nx−1 for each combination of file w, 1≤w≤Nw, column y, 1<y<Ny−1, and row z, 1≤z≤Nz−1;

wherein an Ny column includes checkbits, each of the check bits in the Ny column being the sum modulo 2 across columns 1 to Ny−1 for each combination of file w, 1≤w≤Nw, rank x, 1≤x≤Nx, and row z, 1≤z≤Nz−1; and

wherein an Nz row includes checkbits, each of the check bits in the Nz row being the sum modulo 2 across rows 1 to Nz−1 for each combination of file w, 1≤w≤Nw, rank x, 1≤x≤Nx, and column y, 1≤y≤Ny.

10. The method of claim 9 , wherein the basic bits comprise the information bits, 0 or more constant bits, additional check bits, or combinations thereof.

11. The method of claim 8 , wherein values of the check bits are further calculated such that the modulo-2 sum across one or more paths through the matrix is 0, a length of each path being equal to the minimum number of files, ranks, columns, and rows; and

each bit of the path not having a same file as any other bit of the path;

each bit of the path not having a same rank as any other bit of the path;

each bit of the path not having a same column as any other bit of the path; and

each bit of the path not having a same row as any other bit of the path.

12. A system comprising:

an encoder and a decoder, each configured to create a low-density parity-check code (LDPC), wherein creating the LDPC comprises:

positioning, using the encoder, coded bits comprising information bits, 0 or more constant bits, and check bits in a three-dimensional matrix having ranks, columns, and rows; and

calculating, using the encoder, the check bits such that a modulo-2 sum across the ranks of all combinations of columns and rows, across the columns of all combinations of ranks and rows, and across the rows of all combinations of ranks and columns is 0; and

the decoder further configured to perform, based at least on the LDPC, error correction in a communication system.

13. The system of claim 12 , wherein the three-dimensional matrix includes basic bits including the information bits, 0 or more constant bits, additional check bits, or combinations thereof arranged in Nx−1 ranks, Ny−1 columns, and Nz−1 rows of the three-dimensional matrix;

wherein an Nx rank includes check bits, each of the check bits in the Nx rank being the sum modulo 2 across ranks 1 to Nx−1 for each combination of column y, 1≤y≤Ny−1, and row z, 1≤z≤Nz−1;

wherein an Ny column includes check bits, each of the check bits in the Ny column being the sum modulo 2 across columns 1 to Ny−1 for each combination of rank x, 1≤x≤Nx, and row z, 1≤z≤Nz−1; and

wherein an Nz row includes check bits, each of the check bits in the Nz row being the sum modulo 2 across rows 1 to Nz−1 for each combination of rank x, 1≤x≤Nx, and column y, 1<y<Ny.

14. The system of claim 13 , wherein values of the check bits are further calculated such that the modulo-2 sum across one or more paths through the matrix is 0, a length of each path being equal to a minimum of the number of ranks, columns, and rows; and

each bit of the path not having a same rank as any other bit of the path;

each bit of the path not having a same column as any other bit of the path; and

each bit of the path not having a same row as any other bit of the path.

15. The system of claim 14 , wherein at least one position defined by a selected rank and a selected row and a selected column is not associated with an information bit, and wherein the encoder is further configured to calculate a check bit for the at least one position using bits located at a diagonal pattern of ranks, columns, and rows.

16. The system of claim 15 , wherein multiple positions defined by certain rank and certain row and column pairs are not associated with any information bit but are associated with check bits.

17. The system of claim 12 , wherein the encoder comprises application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), processors, or combinations thereof.

18. The system of claim 12 , further comprising:

a modulator, communicatively coupled to the code generator, and configured to convert the information bits and the check bits into one or more analog baseband waveforms wherein each of the one or more analog baseband waveforms occurs once for a first set of information bits of the information bits and the check bits.

19. The system of claim 18 , further comprising an antenna, an up-converter, an amplifier, and the modulator, or combinations thereof, coupled between the antenna and the encoder, wherein:

the up-converter is configured to convert each of the one or more analog baseband waveforms into a radio frequency (RF) signal,

the amplifier is configured to increase an amplitude of the RF signal into a high-power RF signal, and

the antenna is configured to radiate the high-power RF signal once for the first set of information bits.

20. A system comprising:

an encoder and a decoder, each configured to create a low-density parity-check code (LDPC), wherein creating the LDPC comprises:

positioning, using the encoder, coded bits comprising information bits, 0 or more constant bits, and check bits in a four-dimensional matrix having files, ranks, columns, and rows; and

calculating, using the encoder, the check bits such that a modulo-2 sum across the files of all combinations of ranks, columns, and rows, across the ranks of all combinations of files, columns, and rows, across the columns of all combinations of files, ranks, and rows, and across the rows of all combinations of files, ranks, and columns is 0; and

the decoder further configured to perform, based at least on the LDPC, error correction in a communication system.

21. The system of claim 20 , wherein the four-dimensional matrix includes basic bits including the information bits, 0 or more constant bits, additional check bits, or combinations thereof arranged in Nw−1 files, Nx−1 ranks, Ny−1 columns, and Nz−1 rows of the four-dimensional matrix;

wherein a Nw file includes check bits, each of the check bits in the Nw file being the sum modulo 2 across files 1 to Nw−1 for each combination of rank x, 1≤x≤Nx−1, column y, 1≤y≤Ny−1, and row z, 1≤z≤Nz−1;

wherein a Nx rank includes check bits, each of the check bits in the Nx rank being the sum modulo 2 across ranks 1 to Nx−1 for each combination of file w, 1≤w≤Nw, column y, 1<y<Ny−1, and row z, 1≤z≤Nz−1;

wherein a Ny column includes check bits, each of the check bits in the Ny column being the sum modulo 2 across columns 1 to Ny−1 for each combination of file w, 1≤w≤Nw, rank x, 1≤x≤Nx, and row z, 1≤z≤Nz−1; and

wherein a Nz row includes check bits, each of the check bits in the Nz row being the sum modulo 2 across rows 1 to Nz−1 for each combination of file w, 1≤w≤Nw, rank x, 1≤x≤Nx, and column y, 1≤y≤Ny.

22. The system of claim 21 , wherein values of the check bits are further calculated such that the modulo-2 sum across one or more paths through the matrix is 0, a length of each path being equal to a minimum number of files, ranks, columns, and rows; and

each bit of the path not having a same file as any other bit of the path;

each bit of the path not having a same rank as any other bit of the path;

each bit of the path not having a same column as any other bit of the path; and

each bit of the path not having a same row as any other bit of the path.

23. The system of claim 22 , wherein at least one position defined by a selected file and a selected rank and a selected row and a selected column is not associated with an information bit, and wherein the encoder is further configured to calculate a check bit for the at least one position using bits located at a diagonal pattern of files, ranks, columns, and rows.