Vertical silicon carbide power MOSFET and IGBT and a method of manufacturing the same
Disclosed is a vertical silicon carbide power MOSFET with a 4H-SiC substrate of n+-type as drain and a 4H-Si C epilayer of n−-type, epitaxially grown on the 4H-SiC substrate acting as drift region and a source region of p++-type, a well region of p-type, a channel region of p-type and a contact region of n++-type implanted into the drift region and a metal gate insulated from the source and drift region by a gate-oxide. A high mobility layer with a vertical thickness in a range 0.1 nm to 50 nm exemplarily in the range of 0.5 nm to 10 nm is provided at the interface between the 4H-SiC epilayer and the gate-oxide.
1. A vertical silicon carbide power MOSFET, comprising:
a drain formed by a 4H-SiC substrate with n+ type doping;
a drift region comprising a 4H-SiC epilayer with n− type doping, the 4H-SiC epilayer being epitaxially grown on the 4H-SiC substrate;
a source region with p++ type doping disposed in the drift region;
a well region with p type doping disposed into the drift region;
a channel region with p type doping disposed into the drift region;
a contact region with n++ type doping disposed into the drift region;
a metal gate insulated from the source region and the drift region by a gate-oxide; and
a high mobility layer comprising a 3C-SiC epilayer, the high mobility layer located at an interface between the 4H-SiC epilayer and the gate-oxide and having a vertical thickness between 0.1 nm to 50 nm.
2. The vertical silicon carbide power MOSFET according to claim 1 , wherein the 4H-SiC substrate is a {001} oriented 4H-SiC substrate.
3. The vertical silicon carbide power MOSFET according to claim 1 , wherein the 4H-SiC epilayer is a {001} oriented 4H-SiC epilayer.
4. The vertical silicon carbide power MOSFET according to claim 1 , wherein the 4H-SiC substrate is a {001} oriented 4H-SiC substrate and the 4H-SiC epilayer is a {001} oriented 4H-SiC epilayer.
5. The vertical silicon carbide power MOSFET according to claim 1 , wherein the high mobility layer is an n type doped layer.
6. The vertical silicon carbide power MOSFET according to claim 1 , wherein the vertical thickness of the high mobility layer is in a range of 0.5 nm to 10 nm.
7. A method of operating the vertical silicon carbide power MOSFET according to claim 1 , the method comprising applying a voltage to the metal gate to cause carriers of the vertical silicon carbide power MOSFET to be transported in the drift region but not in the high mobility layer.
8. A vertical silicon carbide power Insulated Gate Bipolar Transistor (IGBT), comprising:
a field stop layer formed by a 4H-SiC substrate with n type doping;
a drift region comprising a 4H-SiC epilayer of n-type, 4H-SiC epilayer having been epitaxially grown the 4H-SiC substrate;
an emitter region of p++ type doping disposed in the drift region;
a well region of p-type doping disposed in the drift region;
a channel region of p-type doping disposed in the drift region;
a contact region with n++ type doping disposed in the drift region;
a metal gate insulated from the emitter region and the drift region by a gate-oxide;
a collector layer of p+ type doping disposed on a surface of the field stop layer, the field stop layer disposed between the drift region and the collector layer; and
a high mobility layer comprising a 3C-Si epilayer located at an interface between the 4H-SiC epilayer and the gate-oxide, wherein the high mobility layer having a vertical thickness between 0.1 nm to 50 nm.
9. The vertical silicon carbide power IGBT according claim 8 , wherein the 4H-SiC substrate is a {001} oriented 4H-SiC substrate and the 4H-SiC epilayer is a {001} oriented 4H-SiC epilayer.
10. The vertical silicon carbide power IGBT according claim 8 , wherein the high mobility layer is an n type doped layer.
11. The vertical silicon carbide power IGBT according claim 8 , wherein the vertical thickness of the high mobility layer is between 0.5 nm to 10 nm.
12. A method of forming a semiconductor device, the method comprising:
epitaxially growing a 4H-SiC epilayer on a 4H-SiC substrate, the 4H-SiC epilayer having n type doping and the 4H-SiC substrate having n type doping;
implanting a first region of p++ type, a second region of p type, a third region of p type and a fourth region of n++ type in a surface of the 4H-SiC epilayer;
epitaxially growing a 3C-SiC layer on the implanted surface of the 4H-SiC epilayer, wherein the 3C-SiC layer is grown to a vertical thickness of 0.1 to 50 nm;
partially oxidizing the 3C-SiC layer;
depositing an insulation layer over the partially oxidized 3C-SiC layer; and
forming a metal region on the insulation layer.
13. The method according to claim 12 , wherein epitaxially growing the 3C-SiC layer comprises performing a chemical vapor deposition (CVD) process.
14. The method according to claim 12 , wherein epitaxially growing the 3C-SiC layer comprises performing metal-organic chemical vapor deposition (MOCVD) process.
15. The method according to claim 12 , wherein epitaxially growing the 3C-SiC layer comprises performing a molecular beam epitaxy (MBE) process.
16. The method according to claim 12 , wherein forming the semiconductor device comprises forming a vertical silicon carbide power MOSFET;
wherein the 4H-SiC substrate has n+ type doping and forms a drain layer;
wherein the 4H-SiC epilayer forms a drift region;
wherein the first region forms a source region;
wherein the second region forms a well region;
wherein the third region forms a channel region;
wherein the fourth region forms a contact region;
wherein the 3C-SiC layer forms a high mobility layer;
wherein the insulation layer forms a gate-oxide; and
wherein the metal region forms a gate region.
17. The method according to claim 16 , further comprising forming an ohmic contact for contacting the source region.
18. The method according to claim 12 , wherein the 4H-SiC epilayer is grown on a first surface of the 4H-SiC substrate, the method further comprising forming a p+ type doped semiconductor layer on a second surface of the 4H-SiC substrate, the second surface opposite the first surface.
19. The method according to claim 18 , wherein forming the semiconductor device comprises forming a vertical silicon carbide power Insulated Gate Bipolar Transistor (IGBT);
wherein the 4H-SiC substrate forms a field stop layer;
wherein the 4H-SiC epilayer forms a drift region;
wherein the p+ type doped semiconductor layer forms a collector layer;
wherein the first region forms an emitter region;
wherein the second region forms a well region;
wherein the third region forms a channel region;
wherein the fourth region forms a contact region;
wherein the 3C-SiC layer forms a high mobility layer;
wherein the insulation layer forms a gate-oxide; and
wherein the metal region forms a gate region.
20. The method according to claim 19 , further comprising forming an ohmic contact for contacting the emitter region.