Temperature sensor circuits for integrated circuit devices
An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.
1. An integrated circuit device, comprising:
a temperature sensor circuit, the temperature sensor circuit including at least one insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure
wherein the temperature sensor circuit provides at least one temperature signal, the at least one temperature signal indicates a temperature window in which the integrated circuit device is operating and the at least one insulated crate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control crate structure has a crate length of less than about 6 nm.
2. The integrated circuit device of claim 1 , wherein:
the temperature sensor circuit includes
an upper window limit comparator circuit coupled to receive a temperature dependent reference potential, the upper window limit comparator circuit detects a temperature window upper limit based on the potential of the temperature dependent reference potential.
3. The integrated circuit device of claim 2 , wherein:
the upper window limit comparator circuit includes the at least one IGFET, the at least one IGFET has a gate terminal coupled to receive the temperature dependent reference potential.
4. The integrated circuit device of claim 3 , wherein:
the upper window limit comparator circuit provides an upper limit detection signal in response to detecting the temperature window upper limit being reached.
5. The integrated circuit device of claim 4 , wherein:
the temperature detector circuit includes a control circuit that changes the state of the at least one temperature signal in response to the upper limit detection signal.
6. The integrated circuit device of claim 1 , wherein:
the temperature sensor circuit includes
a lower window limit comparator circuit coupled to receive a temperature dependent reference potential, the lower window limit comparator circuit detects a temperature window lower limit based on the potential of the temperature dependent reference potential.
7. The integrated circuit device of claim 6 , wherein:
the lower window limit comparator circuit includes the at least one IGFET, the at least one IGFET has a gate terminal coupled to receive the temperature dependent reference potential.
8. The integrated circuit device of claim 6 , wherein:
the lower window limit comparator circuit provides a lower limit detection signal in response to detecting the temperature window lower limit being reached.
9. The integrated circuit device of claim 8 , further including:
the temperature detector circuit includes a control circuit that changes the state of the at least one temperature signal in response to the lower limit detection signal.
10. The integrated circuit device of claim 1 , further including:
the temperature detector circuit includes a reference generator circuit, the reference generator circuit includes the at least one IGFET and provides a temperature dependent reference potential.
11. The integrated circuit device of claim 10 , wherein:
the reference generator circuit provides an essentially temperature independent reference potential.
12. The integrated circuit device of claim 1 , wherein:
a refresh control circuit coupled to receive the at least one temperature signal, the refresh control circuit sets a refresh rate in response to the at least one temperature signal wherein
the integrated circuit device is a dynamic random access memory device.
13. The integrated circuit device of claim 1 , wherein:
a read assist control circuit coupled to receive the at least one temperature signal, the read assist control circuit enables and disables a read assist circuit in response to the at least one temperature signal, the read assist circuit assists a read operation of static random access memory cells formed on the integrated circuit device.
14. The integrated circuit device of claim 1 , wherein:
a write assist control circuit coupled to receive the at least one temperature signal, the write assist control circuit enables and disables a write assist circuit in response to the at least one temperature signal, the write assist circuit assists a write operation of data to static random access memory cells formed on the integrated circuit device.
15. The integrated circuit device of claim 1 , further including:
a semiconductor substrate providing a first region;
a second region formed over the first region;
the at least one insulated gate field effect transistor (IGFET) is formed in the second region; and
at least one active circuit element of the temperature sensor circuit is formed in the first region and electrically connected to the at least one IGFET.
16. The integrated circuit device of claim 15 , wherein:
the at least one active circuit element is a p-n junction diode having an anode terminal electrically connected to the at least one IGFET.
17. The integrated circuit device of claim 1 , wherein:
the at least one insulated gate field effect transistor (IGFET) including at least four substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure, the at least four substantially horizontally disposed channels are electrically connected to a common source region.
18. An integrated circuit device, comprising:
a temperature sensor circuit, the temperature sensor circuit including at least one insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure wherein the temperature sensor circuit provides at least one temperature signal, the at least one temperature signal indicates a temperature window in which the integrated circuit device is operating; and
a frequency control circuit coupled to receive the at least one temperature signal, the frequency control circuit sets the frequency of a clock signal in response to the at least one temperature signal and the integrated circuit device includes processor circuitry coupled to receive the clock signal.
19. The integrated circuit device of claim 18 , wherein:
the at least one insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure has a gate length of less than about 6 nm.
20. An integrated circuit device, comprising:
a temperature sensor circuit, the temperature sensor circuit including at least one insulated gate field effect transistor (IGFET) including at least three substantially horizontally disposed channels that are substantially vertically aligned and surrounded by a contiguous control gate structure wherein the temperature sensor circuit provides at least one temperature signal, the at least one temperature signal indicates a temperature window in which the integrated circuit device is operating; and
a power up circuit, the power up circuit provides a power up signal having a power up logic level in response to detecting power received by the integrated circuit device, the temperature sensor circuit coupled to receive the power up signal and provides a predetermined state to the at least one temperature signal in response to the power up signal.