Data transmission method and apparatus in tee systems
Examples of a data transmission method and apparatus in TEE systems are described. One example of the method includes: obtaining first data; obtaining a write offset address by reading a first address; obtaining a read offset address by reading a second address; determining whether the number of bytes in the first data is less than or equal to the number of writable bytes, where the number of writable bytes is determined based on the write offset address and the read offset address, and each address corresponds to one byte; when the number of bytes in the first data is less than or equal to the number of writable bytes, writing the first data into third addresses starting from the write offset address; and updating the write offset address in the first address.
1. A computer-implemented method for exchanging data in a trusted execution environment (TEE) system, comprising:
obtaining data by a thread running on a TEE side of the TEE system, wherein the TEE system also comprises a non-TEE side and a shared memory, the shared memory comprising a first address, a second address, and multiple consecutive third addresses;
obtaining, by the thread, a write offset address by reading the first address, the write offset address indicating a writable start address in the multiple consecutive third addresses;
obtaining, by the thread, a read offset address by reading the second address, the read offset address indicating a readable start address in the multiple consecutive third addresses;
determining, by the thread, whether a number of bytes in the data is less than or equal to a number of writable bytes, wherein the number of writable bytes is determined based on the write offset address and the read offset address, and wherein each address corresponds to one byte; and
in response to determining that the number of bytes in the data is less than or equal to the number of writable bytes, writing, by the thread, the data into at least a portion of the multiple consecutive third addresses starting from the write offset address.
2. The computer-implemented method of claim 1 , further comprising:
in response to determining that the number of bytes in the data is greater than the number of writable bytes, waiting until the number of bytes in the data is less than or equal to the number of writable bytes.
3. The computer-implemented method of claim 1 , wherein the shared memory further comprises a fourth address that stores a quantity of discarded data, and wherein the method further comprises:
in response to determining that the number of bytes in the data is greater than the number of writable bytes, discarding the data; and
increasing the quantity of discarded data stored in the fourth address by one.
4. The computer-implemented method of claim 3 , wherein the quantity of discarded data is an atomic variable.
5. The computer-implemented method of claim 1 , wherein the write offset address is before the read offset address in the shared memory, and wherein the number of writable bytes is equal to a difference between the read offset address and the write offset address.
6. The computer-implemented method of claim 1 , wherein the write offset address is after the read offset address in the shared memory, wherein the number of writable bytes is equal to a difference between a number of the multiple consecutive third addresses and a number of non-writable bytes, and wherein the number of non-writable bytes is equal to a difference between the write offset address and the read offset address.
7. The computer-implemented method of claim 1 , wherein the write offset address is the same as the read offset address, and wherein the number of writable bytes is equal to a number of the multiple consecutive third addresses.
8. A non-transitory, computer-readable medium storing one or more instructions that, when executed by a computer system of a trusted execution environment (TEE) system, cause the computer system to perform operations for exchanging data in the TEE system, wherein the operations comprise:
obtaining data by a thread running on a TEE side of the TEE system, wherein the TEE system also comprises a non-TEE side and a shared memory, the shared memory comprising a first address, a second address, and multiple consecutive third addresses;
obtaining, by the thread, a write offset address by reading the first address, the write offset address indicating a writable start address in the multiple consecutive third addresses;
obtaining, by the thread, a read offset address by reading the second address, the read offset address indicating a readable start address in the multiple consecutive third addresses;
determining, by the thread, whether a number of bytes in the data is less than or equal to a number of writable bytes, wherein the number of writable bytes is determined based on the write offset address and the read offset address, and wherein each address corresponds to one byte; and
in response to determining that the number of bytes in the data is less than or equal to the number of writable bytes, writing, by the thread, the data into at least a portion of the multiple consecutive third addresses starting from the write offset address.
9. The non-transitory, computer-readable medium of claim 8 , wherein the operations further comprise:
in response to determining that the number of bytes in the data is greater than the number of writable bytes, waiting until the number of bytes in the data is less than or equal to the number of writable bytes.
10. The non-transitory, computer-readable medium of claim 8 , wherein the shared memory further comprises a fourth address that stores a quantity of discarded data, and wherein the operations further comprise:
in response to determining that the number of bytes in the data is greater than the number of writable bytes, discarding the data; and
increasing the quantity of discarded data stored in the fourth address by one.
11. The non-transitory, computer-readable medium of claim 10 , wherein the quantity of discarded data is an atomic variable.
12. The non-transitory, computer-readable medium of claim 8 , wherein the write offset address is before the read offset address in the shared memory, and wherein the number of writable bytes is equal to a difference between the read offset address and the write offset address.
13. The non-transitory, computer-readable medium of claim 8 , wherein the write offset address is after the read offset address in the shared memory, wherein the number of writable bytes is equal to a difference between a number of the multiple consecutive third addresses and a number of non-writable bytes, and wherein the number of non-writable bytes is equal to a difference between the write offset address and the read offset address.
14. The non-transitory, computer-readable medium of claim 8 , wherein the write offset address is the same as the read offset address, and wherein the number of writable bytes is equal to a number of the multiple consecutive third addresses.
15. A computer-implemented system, comprising:
one or more computers of a trusted execution environment (TEE) system; and
one or more computer memory devices interoperably coupled with the one or more computers and having tangible, non-transitory, machine-readable media storing one or more instructions that, when executed by the one or more computers, cause the one or more computers to perform one or more operations for exchanging data in the TEE system, wherein the operations comprise:
obtaining data by a thread running on a TEE side of the TEE system, wherein the TEE system also comprises a non-TEE side and a shared memory, the shared memory comprising a first address, a second address, and multiple consecutive third addresses;
obtaining, by the thread, a write offset address by reading the first address, the write offset address indicating a writable start address in the multiple consecutive third addresses;
obtaining, by the thread, a read offset address by reading the second address, the read offset address indicating a readable start address in the multiple consecutive third addresses;
determining, by the thread, whether a number of bytes in the data is less than or equal to a number of writable bytes, wherein the number of writable bytes is determined based on the write offset address and the read offset address, and wherein each address corresponds to one byte; and
in response to determining that the number of bytes in the data is less than or equal to the number of writable bytes, writing, by the thread, the data into at least a portion of the multiple consecutive third addresses starting from the write offset address.
16. The computer-implemented system of claim 15 , wherein the operations further comprise:
in response to determining that the number of bytes in the data is greater than the number of writable bytes, waiting until the number of bytes in the data is less than or equal to the number of writable bytes.
17. The computer-implemented system of claim 15 , wherein the shared memory further comprises a fourth address that stores a quantity of discarded data, and wherein the operations further comprise:
in response to determining that the number of bytes in the data is greater than the number of writable bytes, discarding the data; and
increasing the quantity of discarded data stored in the fourth address by one.
18. The computer-implemented system of claim 17 , wherein the quantity of discarded data is an atomic variable.
19. The computer-implemented system of claim 15 , wherein the write offset address is before the read offset address in the shared memory, and wherein the number of writable bytes is equal to a difference between the read offset address and the write offset address.
20. The computer-implemented system of claim 15 , wherein the write offset address is after the read offset address in the shared memory, wherein the number of writable bytes is equal to a difference between a number of the multiple consecutive third addresses and a number of non-writable bytes, and wherein the number of non-writable bytes is equal to a difference between the write offset address and the read offset address.
21. The computer-implemented system of claim 15 , wherein the write offset address is the same as the read offset address, and wherein the number of writable bytes is equal to a number of the multiple consecutive third addresses.