SYSTEM AND METHOD FOR CONFIGURABLE AND DISTRIBUTED PROCESSING FOR QUANTUM CONTROL

1 . A system comprising:

a first quantum controller (QC) operable to a generate a first data vector and an instruction; and

a second QC comprising a non-deterministic hardware circuit, wherein the non-deterministic hardware circuit is operable to generate a second data vector according to the first data vector and the instruction.

2 . The system of claim 1 , wherein the non-deterministic hardware circuit is operable to serve a plurality of pulse processors.

3 . The system of claim 2 , wherein the non-deterministic hardware circuit resides externally to the plurality of pulse processors.

4 . The system of claim 1 , wherein the first QC and the second QC are operable to communicate asynchronously via a SERDES and an external interaction hardware circuit.

5 . The system of claim 1 , wherein the non-deterministic hardware circuit may operate on a stream of data arriving from a deterministic hardware circuit.

6 . The system of claim 5 , wherein the stream of data is associated with a qubit state.

7 . The system of claim 1 , wherein the non-deterministic hardware is operable to process a stream of data from an external interaction hardware circuit.

8 . The quantum controller of claim 7 , wherein the external interaction hardware circuit is operable to receive an external inbound stream of data, and wherein the external inbound stream of data is one of digital and analog.

9 . The system of claim 1 , wherein the non-deterministic hardware comprises one or more of a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence (AI) engine, an offload acceleration engine (OAE) and a direct memory access (DMA) engine.

10 . The system of claim 9 , wherein the DMA engine is operable to read program data from an external device in real time, and wherein the quantum controller is operable to be dynamically reconfigured, and wherein the quantum controller is operable to run a contentious complex program regardless of on-chip memory resources.

11 . The system of claim 1 , wherein the second QC comprises one or more pulse processors.

12 . The system of claim 11 , wherein at least one of the one or more pulse processors comprises the non-deterministic hardware circuit.

13 . The system of claim 11 , wherein the at least one pulse processor comprises external interaction hardware circuit, and wherein the non-deterministic hardware circuit of the at least one pulse processor in the second QC is operable to receive the first data vector via the external interaction hardware circuit.

14 . The system of claim 13 , wherein the external interaction hardware circuit is operable to write directly to a memory associated with the non-deterministic hardware circuit.

15 . The quantum controller of claim 11 , wherein the one or more pulse processors comprises an external interaction hardware circuit operable to receive the first data vector from an external source, and wherein the external source is one of digital and analog.

16 . The system of claim 1 , wherein the non-deterministic hardware circuit is configured according to metadata that is written directly to a memory associated with the non-deterministic hardware circuit.

17 . The system of claim 16 , wherein the memory is periodically polled by the non-deterministic hardware circuit.

18 . The system of claim 1 , wherein the system comprises a QC switch operably coupled to the first QC and the second QC.

19 . The system of claim 1 , wherein the first QC is operable to dispatch the first data vector to a pulse processor in the second QC.

20 . A method for quantum computing, the method comprising:

generating, via a first quantum controller (QC), a first data vector and an instruction; and

generating, via a non-deterministic hardware circuit of a second QC, a second data vector according to the first data vector and the instruction.

21 . The method of claim 20 , wherein the non-deterministic hardware circuit is operable to serve a plurality of pulse processors.

22 . The method of claim 21 , wherein the non-deterministic hardware circuit resides externally to the plurality of pulse processors.

23 . The method of claim 20 , wherein the method comprises communicating asynchronously, between the first QC and the second QC, via a SERDES and an external interaction hardware circuit.

24 . The method of claim 20 , wherein the method comprises operating, via the non-deterministic hardware circuit, on a stream of data arriving from a deterministic hardware circuit.

25 . The method of claim 24 , wherein the stream of data is associated with a qubit state.

26 . The method of claim 20 , wherein the second QC comprises one or more pulse processors.

27 . The method of claim 26 , wherein at least one of the one or more pulse processors comprises the non-deterministic hardware circuit.

28 . The method of claim 26 , wherein the at least one pulse processor comprises external interaction hardware circuit, and wherein the method comprises receiving the first data vector, by the non-deterministic hardware circuit, via the external interaction hardware circuit.

29 . The method of claim 28 , wherein the method comprises writing, via the external interaction hardware circuit, directly to a memory associated with the non-deterministic hardware circuit.

30 . The method of claim 20 , wherein the method comprises configuring the non-deterministic hardware circuit according to metadata that is written directly to a memory associated with the non-deterministic hardware circuit.

31 . The method of claim 30 , wherein the method comprises periodically polling the memory with the non-deterministic hardware circuit.

32 . The method of claim 20 , wherein a QC switch is operably coupled to the first QC and the second QC.

33 . The method of claim 20 , wherein the method comprises dispatching the first data vector from the first QC to a pulse processor in the second QC.