Write training in memory devices by adjusting delays based on data patterns

1. A memory device comprising:

a plurality of input/output (I/O) nodes to receive a plurality of periods of a predefined data pattern;

a circuit to adjust a delay for each I/O node as the predefined data pattern is received;

a latch to latch the data received on each I/O node in response to a data strobe signal;

a memory to store the latched data; and

control logic to:

sweep, via the circuit, the delay for each I/O node to adjust a signal edge for each I/O node as the predefined data pattern is received;

compare the stored latched data to an expected data pattern;

generate a table indicating which stored latched data for each I/O node for each period of the predefined data pattern matches the expected data pattern for each I/O node and which stored latched data for each I/O node for each period of the predefined data pattern does not match the expected data pattern for each I/O node; and

adjust setup and hold time margins for each I/O node by setting, via the circuit, the delay for each I/O node based on the table indicating which stored latched data for each I/O node for each period of the predefined data pattern matches the expected data pattern for each I/O node.

2. The memory device of claim 1 , further comprising:

a deserializer to convert serial data from the latch to parallel data for storage in the memory.

3. The memory device of claim 1 , wherein the circuit is to adjust a delay of the data strobe signal used to latch the data as the predefined data pattern is received; and

wherein the control logic is to set the delay of the data strobe signal based on the table.

4. The memory device of claim 1 , wherein the circuit comprises a state machine.

5. The memory device of claim 1 , further comprising:

a pattern generator to generate the expected data pattern.

6. The memory device of claim 1 , further comprising:

an XOR circuit to compare the stored latched data to the expected data pattern.

7. A method for write training in a memory device, the method comprising:

receiving input data comprising a predefined pattern at the memory device;

analyzing eye openings for the received data within the memory device; and

adjusting setup and hold time margins within the memory device based on the analysis, wherein analyzing the eye openings for the received data comprises:

sweeping a delay value within the memory device to adjust a signal edge for each input/output (I/O) node of the memory device as the predefined pattern is received;

latching the input data in response to a data strobe signal;

storing the latched input data in the memory device;

comparing the stored input data to an expected data pattern; and

generating a table indicating which stored data for each I/O node for each period of the predefined data pattern matches the expected data pattern for each I/O node and which stored data for each I/O node for each period of the predefined data pattern does not match the expected data pattern for each I/O node, and

wherein adjusting the setup and hold time margins comprises setting a delay value for each I/O node based on the table indicating which stored data for each I/O node for each period of the predefined data pattern matches the expected data pattern for each I/O node.

8. The method of claim 7 , wherein adjusting the setup and hold time margins of the memory device comprises individually adjusting the setup and hold time margin for each input/output (I/O) node of the memory device.

9. The method of claim 8 , wherein adjusting the setup and hold time margin for each I/O node of the memory device comprises aligning the latching of input data for each I/O node.

10. The method of claim 8 , wherein adjusting the setup and hold time margin for each I/O node of the memory device comprises individually setting a delay for each I/O node.

11. The method of claim 7 , wherein adjusting the setup and hold time margins of the memory device comprises adjusting an edge of a data strobe signal used to latch the input data.

12. The method of claim 7 , further comprising:

storing the table in a volatile memory of the memory device.

13. A method for write training in a memory device, the method comprising:

receiving a periodic predefined data pattern via a plurality of input/output (I/O) nodes of the memory device;

receiving a data strobe signal via a data strobe signal node of the memory device;

latching data received by each I/O node in response to the data strobe signal;

adjusting a delay for each I/O node after each period of the predefined data pattern is received to adjust a signal edge for each I/O node;

storing the latched data in the memory device;

comparing the stored data for each I/O node for each period of the predefined data pattern to an expected data pattern for each I/O node;

generating a table indicating which stored data for each I/O node for each period of the predefined data pattern matches the expected data pattern for each I/O node and which stored data for each I/O node for each period of the predefined data pattern does not match the expected data pattern for each I/O node; and

adjusting setup and hold time margins for each I/O node by setting the delay for each I/O node based on the table indicating which stored data for each I/O node for each period of the predefined data pattern matches the expected data pattern for each I/O node.

14. The method of claim 13 , further comprising:

storing the table in a volatile memory of the memory device.

15. The method of claim 13 , wherein setting the delay for each I/O node comprises setting the delay for each I/O node to align the latching of data received by each I/O node.

16. The method of claim 13 , further comprising:

adjusting a delay for the data strobe signal after a plurality of periods of the predefined data pattern is received; and

setting the delay of the data strobe signal based on the comparison to maximize setup and hold time margins for data received by each I/O node.