IP Library Granted Patent US 11,539,973
Granted Patent B2
US 11,539,973 · App. 17/317,629 · Granted Dec 27, 2022

Method and device for processing video signal using multiple transform kernels

Inventors: Jaehong Jung (Seoul, KR); Juhyung Son (Uiwang-Si, KR); Dongcheol Kim (Suwon-Si, KR); Geonjung Ko (Seoul, KR); Jinsam Kwak (Anyang-Si, KR)
Assignee: HUMAX CO., LTD.
H04N19/46H04N19/119H04N19/159H04N19/176H04N19/60
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Quick Facts
Patent No.
US 11,539,973
App. No.
17/317,629
Granted
Dec 27, 2022
Kind
B2
Abstract

A method for processing a video signal comprises the steps of: obtaining, from the video signal, an intra sub-partitions (ISP) mode flag indicating whether the ISP mode is applied to a current block; when the ISP mode is applied to the current block, obtaining, from the video signal, an ISP partitioning flag indicating a partitioning direction of the current block; partitioning the current block into a plurality of transform blocks on the basis of the partitioning direction; generating residual blocks of the transform blocks by performing an inverse transformation on each of the transform blocks; and restoring the current block on the basis of the residual blocks.

Claims (56)

1. A non-transitory computer-readable medium storing a bitstream, the bitstream being decoded by a decoding method,

wherein the decoding method, comprising:

obtaining an intra sub-partitions (ISP) mode flag indicating whether or not an ISP mode is applied to a current block from a video signal;

if the ISP mode is applied to the current block, obtaining an ISP partitioning flag indicating a partitioning direction of the current block from the video signal;

partitioning the current block into a plurality of transform blocks on the basis of the partitioning direction;

generating residual blocks of the transform blocks by performing inverse transformation on each of the transform blocks; and

reconstructing the current block on the basis of the residual blocks,

wherein the generating the residual blocks comprises:

determining a horizontal transform type applied in a horizontal direction of a current transform block from among a plurality of predefined transform types on the basis of a width of the current transform block regardless of an intra prediction mode of the current block;

determining a vertical transform type applied in a vertical direction of the current transform block from among the plurality of predefined transform types on the basis of a height of the current transform block regardless of the intra prediction mode of the current block; and

performing inverse transformation on the current transform block using the horizontal transform type and the vertical transform type.

2. The non-transitory computer-readable medium storing the bitstream of claim 1 , wherein the determining the horizontal transform type comprises:

if the width of the current transform block is less than a first threshold or greater than a second threshold, determining the horizontal transform type to be a first transform type; and

if the width of the current transform block is greater than or equal to the first threshold and less than or equal to the second threshold, determining the horizontal transform type to be a second transform type, and

wherein the determining the vertical transform type comprises:

if the height of the current transform block is less than the first threshold or greater than the second threshold, determining the vertical transform type to be the first transform type; and

if the height of the current transform block is greater than or equal to the first threshold and less than or equal to the second threshold, determining the vertical transform type to be the second transform type.

3. The non-transitory computer-readable medium storing the bitstream of claim 2 , wherein the first transform type is defined as a transform kernel based on a discrete cosine transform type-2 (DCT-2), and the second transform type is defined as a transform kernel based on a discrete sine transform type-7 (DST-7).

4. The non-transitory computer-readable medium storing the bitstream of claim 2 , wherein the first threshold is defined on the basis of a minimum transform block size of a luma component.

5. The non-transitory computer-readable medium storing the bitstream of claim 2 , wherein the second threshold is defined on the basis of a maximum size of the second transform type used in the ISP mode.

6. The non-transitory computer-readable medium storing the bitstream of claim 2 , wherein the first threshold is defined as 4, and the second threshold is defined as 16.

7. The non-transitory computer-readable medium storing the bitstream of claim 1 , wherein the horizontal transform type is determined on the basis of the width of the current transform block regardless of the height of the current transform block, and

wherein the vertical transform type is determined on the basis of the height of the current transform block regardless of the width of the current transform block.

8. A video signal decoding device comprising a processor,

wherein the processor is configured to:

obtain an intra sub-partitions (ISP) mode flag indicating whether or not an ISP mode is applied to a current block from a video signal;

if the ISP mode is applied to the current block, obtain an ISP partitioning flag indicating a partitioning direction of the current block from the video signal;

partition the current block into a plurality of transform blocks on the basis of the partitioning direction;

generate residual blocks of the transform blocks by performing inverse transformation on each of the transform blocks; and

reconstruct the current block on the basis of the residual blocks, and

wherein the processor is further configured to:

determine a horizontal transform type applied in a horizontal direction of a current transform block from among a plurality of predefined transform types on the basis of a width of the current transform block regardless of an intra prediction mode of the current block;

determine a vertical transform type applied in a vertical direction of the current transform block from among the plurality of predefined transform types on the basis of a height of the current transform block regardless of the intra prediction mode of the current block; and

generate a residual block by performing inverse transformation on the current transform block using the horizontal transform type and the vertical transform type.

9. The video signal decoding device of claim 8 , wherein the processor is configured to:

if the width of the current transform block is less than a first threshold or greater than a second threshold, determine the horizontal transform type to be a first transform type;

if the width of the current transform block is greater than or equal to the first threshold and less than or equal to the second threshold, determine the horizontal transform type to be a second transform type;

if the height of the current transform block is less than the first threshold or greater than a second threshold, determine the vertical transform type to be the first transform type; and

if the height of the current transform block is greater than or equal to the first threshold and less than or equal to the second threshold, determine the vertical transform type to be the second transform type.

10. The video signal decoding device of claim 9 , wherein the first transform type is defined as a transform kernel based on a discrete cosine transform type-2 (DCT-2), and the second transform type is defined as a transform kernel based on a discrete sine transform type-7 (DST-7).

11. The video signal decoding device of claim 9 , wherein the first threshold is defined on the basis of a minimum transform block size of a luma component.

12. The video signal decoding device of claim 9 , wherein the second threshold is defined on the basis of a maximum size of the second transform type used in the ISP mode.

13. The video signal decoding device of claim 9 , wherein the first threshold is defined as 4, and the second threshold is defined as 16.

14. The video signal decoding device of claim 8 , wherein the horizontal transform type is determined on the basis of the width of the current transform block regardless of the height of the current transform block, and

wherein the vertical transform type is determined on the basis of the height of the current transform block regardless of the width of the current transform block.

15. A video signal encoding device comprising a processor,

wherein the processor is configured to:

encode an intra sub-partitions (ISP) mode flag indicating whether or not an ISP mode is applied to a current block;

if the ISP mode is applied to the current block, encode an ISP partitioning flag indicating a partitioning direction of the current block;

partition the current block into a plurality of blocks on the basis of the partitioning direction;

generate a transform block of the partitioned blocks by performing transformation of a residual signal of the partitioned blocks; and

generate a bitstream by encoding the transform block,

wherein the processor is further configured to:

determine a horizontal transform type applied in a horizontal direction of a current transform block from among a plurality of predefined transform types on the basis of a width of the current transform block regardless of an intra prediction mode of the current block;

determine a vertical transform type applied in a vertical direction of the current transform block from among the plurality of predefined transform types on the basis of a height of the current transform block regardless of the intra prediction mode of the current block; and

perform transformation on the current transform block using the horizontal transform type and the vertical transform type.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECORD BY REPLACING THE PREVIOUSLY RECORDED CONFIDENTIAL PURCHASE AGREEMENT PREVIOUSLY RECORDED ON REEL 73239 FRAME 166. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 26, 2026
From: HUMAX CO., LTD.
To: ADVEXT IP LLC
Reel/Frame 075743/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2026
From: ADVEXT IP LLC
To: VIDAXIO LLC
Reel/Frame 074323/0501 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2025
From: HUMAX CO., LTD.
To: ADVEXT IP LLC
Reel/Frame 073239/0166 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2022
From: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC.
To: HUMAX CO., LTD.
Reel/Frame 060456/0131 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2021
From: JUNG, JAEHONG; SON, JUHYUNG; KIM, DONGCHEOL; KO, GEONJUNG; KWAK, JINSAM
To: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC.; HUMAX CO., LTD.
Reel/Frame 056205/0797 →
Priority Claims (4)
KR 10-2019-0004278 · Jan 12, 2019 · national
KR 10-2019-0007044 · Jan 18, 2019 · national
KR 10-2019-0027876 · Mar 12, 2019 · national
KR 10-2019-0036421 · Mar 29, 2019 · national
Continuity (2)
Continuation PCTKR2020000638 · Jan 13, 2020
Related Publication 20210266581A1 · Aug 26, 2021