Multi-threaded, self-scheduling reconfigurable computing fabric
Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.
1. An apparatus comprising:
a configurable circuit of a plurality of configurable circuits, each configurable circuit comprising:
a configurable computation circuit;
a plurality of synchronous network inputs;
a plurality of synchronous network outputs; and
a configuration memory coupled to the configurable computation circuit, to the plurality of synchronous network inputs, and to the plurality of synchronous network outputs, the configuration memory comprising:
a first instruction memory configured to store a first plurality of configuration instructions to configure the configurable computation circuit; and
a second instruction memory configured to store a second plurality of configuration instructions or instruction indices for selection of a configuration instruction of the first plurality of configuration instructions from the first instruction memory and for selection of a master synchronous network input of the plurality of synchronous network inputs for receipt of the configuration instruction or a configuration instruction index from an adjacent configurable circuit of the plurality of configurable circuits.
2. The apparatus of claim 1 , wherein each configuration instruction or instruction index of the second plurality of configuration instructions or instruction indices for selection of the configuration instruction of the first plurality of configuration instructions from the first instruction memory is selected according to a predetermined cadence or count for instruction execution by the configurable computation circuit.
3. The apparatus of claim 1 , wherein the second plurality of configuration instructions or instruction indices further comprises instructions or instruction indices for selection of a next configuration instruction or index for output to the master synchronous network input of a next configurable circuit of the plurality of configurable circuits.
4. The apparatus of claim 3 , further comprising:
a conditional logic circuit coupled to the configurable computation circuit, the conditional logic circuit configured, depending upon an output from the configurable computation circuit, to modify the next configuration instruction or instruction index to output a modified next configuration instruction or index to the master synchronous network input of the next configurable circuit.
5. The apparatus of claim 1 , wherein the second plurality of configuration instructions or instruction indices further comprises instructions or instruction indices for selection of a synchronous network output of the plurality of synchronous network outputs.
6. The apparatus of claim 1 , further comprising:
an asynchronous network input queue coupled to an asynchronous packet network, the asynchronous network input queue configured to receive a first asynchronous network message or packet from the asynchronous packet network;
an asynchronous network output queue, the asynchronous network output queue configured to transfer a second asynchronous network message or packet for routing on the asynchronous packet network;
a stop signal communication line coupled to each of the configurable circuits of the plurality of configurable circuits; and
a flow control circuit coupled to the asynchronous network output queue, the flow control circuit configured to generate a stop signal on the stop signal communication line when a predetermined threshold has been reached in the asynchronous network output queue;
wherein, in response to receipt of the stop signal, each configurable circuit of the plurality of configurable circuits is configured to pause execution while continuing to receive one or more third asynchronous network messages or packets routed from the asynchronous packet network.
7. The apparatus of claim 1 , further comprising:
a control circuit coupled to the configurable computation circuit, the control circuit comprising:
a thread control circuit; and
a plurality of control registers configured to store a completion table having a plurality of thread identifiers and, for each thread identifier of a current thread, further having an identification of a last iteration or a thread identifier identifying a next thread for execution following execution of the current thread.
8. The apparatus of claim 1 , further comprising:
a control circuit coupled to the configurable computation circuit, the control circuit comprising:
a plurality of control registers configured to store a completion table having a plurality of thread identifiers and having a corresponding data completion count for each thread identifier of the plurality of thread identifiers; and
a thread control circuit configured to self-schedule and queue a selected thread for execution when, for the thread identifier for the selected thread, of the plurality of thread identifiers, the corresponding data completion count has decremented to zero.
9. The apparatus of claim 1 , further comprising:
a control circuit coupled to the configurable computation circuit, the control circuit comprising:
a plurality of control registers configured to store a completion table having a plurality of thread identifiers, having a corresponding data completion count for each thread identifier of the plurality of thread identifiers and, for each thread identifier for a current thread of the plurality of thread identifiers, having an identification of a last iteration or another thread identifier identifying a next thread for execution following execution of the current thread; and
a thread control circuit configured to self-schedule and queue a selected thread for execution when, for the thread identifier for the selected thread, the corresponding data completion count has decremented to zero and the thread identifier for the selected thread is identified as the next thread for execution.
10. The apparatus of claim 1 , further comprising:
a control circuit coupled to the configurable computation circuit, the control circuit comprising:
a thread control circuit; and
a plurality of control registers configured to store a completion table having a plurality of types of thread identifiers, with each type of thread identifier indicating a loop level for loop and nested loop execution, and wherein the plurality of control registers are further configured to store a top of thread identifiers stack to allow each type of thread identifier access to private variables for a selected loop.
11. The apparatus of claim 1 , further comprising:
a thread control circuit comprising:
a first queue configured to store one or more computation threads or thread identifiers for one or more computation threads which are ready to execute;
a second queue configured to store one or more thread identifiers for computation threads having data completion counts allowing execution or configured to store computation threads without an assigned thread identifier; and
a third queue configured to store one or more computation threads or thread identifiers for computation threads having data completion counts allowing execution to provide for continuing execution of the threads in the third queue upon a designated count by moving the computation threads or the one or more thread identifiers in the third queue into the first queue ahead of any computation threads or the one or more thread identifiers in the second queue.
12. The apparatus of claim 1 , further comprising:
an asynchronous network input queue coupled to an asynchronous packet network;
an asynchronous network output queue coupled to the asynchronous packet network; and
a control circuit coupled to the configurable computation circuit, the control circuit comprising:
a plurality of control registers configured to store a thread identifier pool and a completion table having a loop count of an active number of loop threads; and
a thread control circuit, wherein in response to receipt of an asynchronous packet network message returning a thread identifier to the thread identifier pool, the control circuit is configured to decrement the loop count and, when the loop count reaches zero, to transmit an asynchronous packet network completion message.
13. The apparatus of claim 1 , wherein each synchronous network input of the plurality of synchronous network inputs is coupled to a corresponding synchronous network output, of the plurality of synchronous network outputs, of one or more adjacent configurable circuits of the plurality of configurable circuits to form a synchronous network, and the apparatus further comprises:
an asynchronous packet network coupled to the plurality of the configurable circuits; and
wherein one or more of the plurality of the configurable circuits are coupled in series through the synchronous network to form a first synchronous domain and one or more of the plurality of the configurable circuits are coupled in series through the synchronous network to form a second synchronous domain, the plurality of configurable circuits configured to perform a plurality of computations using the first and second synchronous domains, and the plurality of configurable circuits further configured to generate and transmit a plurality of control messages over the asynchronous packet network, the plurality of control messages comprising one or more completion messages and one or more continue messages.
14. The apparatus of claim 1 , wherein one or more configurable circuits of the plurality of the configurable circuits are arranged in an array, and the apparatus further comprises:
an interconnection network;
a processor coupled to the interconnection network; and
an asynchronous packet network coupled to each configurable circuit of the one or more configurable circuits of the array.
15. The apparatus of claim 1 , wherein one or more configurable circuits of the plurality of the configurable circuits are arranged in an array, and the apparatus further comprises:
a hierarchical interconnection network comprising a first plurality of crossbar switches having a Folded Clos configuration and a plurality of direct, mesh connections at interfaces with endpoints;
a processor coupled to the hierarchical interconnection network;
an asynchronous packet network comprising a second plurality of crossbar switches, each crossbar switch coupled to at least one configurable circuit of the array of the one or more configurable circuits and to another crossbar switch of the second plurality of crossbar switches;
a memory interface coupled to the asynchronous packet network and to the interconnection network;
a dispatch interface coupled to the asynchronous packet network and to the interconnection network; and
a synchronous network coupling each synchronous network input of the plurality of synchronous network inputs to a corresponding synchronous network output, of the plurality of synchronous network outputs, of one or more adjacent configurable circuits of the plurality of configurable circuits to form a plurality of direct connections between adjacent configurable circuits of the array of the one or more configurable circuits, and wherein the synchronous network further comprises at least one pass through connection between adjacent configurable circuits of the array of the one or more configurable circuits.
16. An apparatus comprising:
an asynchronous packet network;
a synchronous network; and
a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits comprising:
a plurality of synchronous network inputs;
a plurality of synchronous network outputs, each synchronous network output of the plurality of synchronous network outputs coupled through the synchronous network to a corresponding synchronous network input, of the plurality of synchronous network inputs, of one or more adjacent configurable circuits of the array plurality of configurable circuits;
a configurable computation circuit; and
a configuration memory coupled to the configurable computation circuit, to the plurality of synchronous network inputs, and to the plurality of synchronous network outputs, the configuration memory comprising:
a first instruction memory configured to store a first plurality of configuration instructions to configure the configurable computation circuit; and
a second instruction memory configured to store a second plurality of configuration instructions or instruction indices for selection of a configuration instruction of the plurality of configuration instructions from the first instruction memory, for selection of a master synchronous network input of the plurality of synchronous network inputs for receipt of the configuration instruction or a configuration instruction index from an adjacent configurable circuit of the array of the plurality of configurable circuits, and for selection of a next configuration instruction or instruction index for output to the master synchronous input of a next configurable circuit of the array of the plurality of configurable circuits.
17. The apparatus of claim 16 , wherein each configurable circuit of the plurality of configurable circuits further comprises:
a control circuit coupled to the configurable computation circuit, the control circuit comprising:
a plurality of control registers configured to store a completion table having a plurality of thread identifiers, having a corresponding data completion count for each thread identifier of the plurality of thread identifiers, having an identification of a first iteration, having an identification of a last iteration, and for each thread identifier for a current thread of the plurality of thread identifiers, having the identification of the last a last iteration or having another thread identifier identifying a next thread for execution following execution of the current thread; and
a thread control circuit configured to self-schedule and queue a selected thread for execution when, for the thread identifier for the selected thread, the corresponding data completion count indicates completion of one or more data dependencies and the thread identifier for the selected thread is identified as the next thread.
18. The apparatus of claim 16 , further comprising:
a conditional logic circuit coupled to the configurable computation circuit, the conditional logic circuit configured, depending upon an output from the configurable computation circuit, to modify the next configuration instruction or instruction index to output a modified next configuration instruction or index to the master synchronous network input of the next configurable circuit.
19. The apparatus of claim 16 , wherein the thread control circuit further comprises:
a first queue configured to store one or more computation threads or thread identifiers for one or more computation threads which are ready to execute;
a second queue configured to store one or more thread identifiers for computation threads having data completion counts allowing execution or configured to store computation threads without an assigned thread identifier; and
a third queue configured to store one or more computation threads or thread identifiers for computation threads having data completion counts allowing execution to provide for continuing execution of the threads in the third queue upon a designated count by moving the computation threads or the one or more thread identifiers in the third queue into the first queue ahead of any computation threads or the one or more thread identifiers in the second queue.
20. An apparatus comprising:
an interconnection network;
a processor coupled to the interconnection network;
an asynchronous packet network;
a synchronous network; and
a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits comprising:
an asynchronous input queue coupled to the asynchronous packet network;
an asynchronous output queue coupled to the asynchronous packet network;
a plurality of synchronous network inputs coupled to the synchronous network;
a plurality of synchronous network outputs coupled to the synchronous network;
a configurable computation circuit; and
a configuration memory coupled to the configurable computation circuit, to the plurality of synchronous network inputs, and to the plurality of synchronous network outputs, the configuration memory comprising:
a first instruction memory configured to store a first plurality of configuration instructions to configure the configurable computation circuit; and
a second instruction memory configured to store a second plurality of configuration instructions or instruction indices for selection of a configuration instruction of the plurality of configuration instructions from the first instruction memory, for selection of a master synchronous network input of the plurality of synchronous network inputs for receipt of the configuration instruction or a configuration instruction index from an adjacent configurable circuit of the array of the plurality of configurable circuits, and for selection of a next configuration instruction or instruction index for output to the master synchronous input of a next configurable circuit of the array of the plurality of configurable circuits.