Integrated display devices
An IC chip includes I/O bumps on a back side, a first die, a second die, a first circuit, and a second circuit. The first die has driver circuits for LED devices, the LED devices being located on a front-facing surface of the first die. The first circuit extends from the front side toward the back side and across a thickness of the first die. The first circuit provides electrical connections between the LED devices and at least some of the I/O bumps. The first die and the second die can be stacked vertically or arranged laterally adjacent. The second circuit extends between the first die and the second die to electrically connect the first die and the second die. A circuit board can be electrically connected to the IC chip through the I/O bumps to, among other things, provide power to the various components of the IC chip.
1. A display apparatus comprising:
an integrated circuit (IC) chip comprising:
input/output (I/O) bumps on a back side of the IC chip;
a first die including driver circuits electrically connected to at least some of the I/O bumps, wherein the driver circuits are configured to generate control signals for light emitting diode (LED) devices located on a surface of the first die that faces a front side of the IC chip;
a first circuit extending from the front side of the IC chip toward the back side of the IC chip and across a thickness of the first die, wherein the first circuit provides electrical connections between the LED devices and at least some of the I/O bumps; and
a second die electrically connected to at least some of the I/O bumps, wherein the first die and the second die are electrically connected through a second circuit extending between the first die and the second die; and
a circuit board electrically connected through the I/O bumps to each of the first die, the second die, and the LED devices.
2. The display apparatus of claim 1 , wherein the second die includes at least one of pipelining circuits or control circuits for the driver circuits of the first die.
3. The display apparatus of claim 1 , wherein the first die is stacked vertically with the second die.
4. The display apparatus of claim 3 , wherein at least one of the first circuit or the second circuit includes through silicon vias (TSVs).
5. The display apparatus of claim 3 , further comprising:
a first shoulder structure abutting the first die along a lateral direction, wherein electrical conduction paths within the first shoulder structure are connected to the first circuit;
a second shoulder structure abutting the second die along the lateral direction, wherein electrical conduction paths within the second shoulder structure are connected to the second circuit; and
additional I/O bumps between the first die and the second die, wherein the additional I/O bumps include an I/O bump sandwiched between the first shoulder structure and the second shoulder structure.
6. The display apparatus of claim 1 , wherein the first die is positioned adjacent to the second die along a lateral direction.
7. The display apparatus of claim 6 , wherein the IC chip includes at chip carrier holding the first die and the second die, and wherein electrical conduction paths of the first circuit extend through the chip carrier.
8. The display apparatus of claim 1 , wherein the IC chip includes at least one of:
a first shoulder structure abutting the first die along a lateral direction, wherein electrical conduction paths within the first shoulder structure are connected to the first circuit; or
a second shoulder structure abutting the second die along the lateral direction, wherein electrical conduction paths within the second shoulder structure are connected to the second circuit.
9. The display apparatus of claim 8 , wherein the IC chip includes one or more fan-out circuits adjacent to the LED devices, each fan-out circuit being configured as a redistribution layer (RDL) that is electrically connected to one end of the electrical conduction paths within the first shoulder structure or electrically connected to one end of the electrical conduction paths within the second shoulder structure.
10. The display apparatus of claim 9 , wherein the one or more fan-out circuits include a fan-out circuit extending over the first shoulder structure or the second shoulder structure.
11. The display apparatus of claim 9 , wherein at least one of the one or more fan-out circuits is electrically connected to the LED devices via an inner layer circuit within the first die.
12. The display apparatus of claim 9 , wherein the one or more fan-out circuits include a fan-out circuit that is part of the second circuit.
13. The display apparatus of claim 8 , wherein the I/O bumps include I/O bumps formed on the first shoulder structure or on the second shoulder structure.
14. An integrated circuit (IC) chip comprising:
input/output (I/O) bumps on a back side of the IC chip;
a first die including driver circuits electrically connected to at least some of the I/O bumps, wherein the driver circuits are configured to generate control signals for light emitting diode (LED) devices located on a surface of the first die that faces a front side of the IC chip;
a first circuit extending from the front side of the IC chip toward the back side of the IC chip and across a thickness of the first die, wherein the first circuit provides electrical connections between the LED devices and at least some of the I/O bumps; and
a second die electrically connected to at least some of the I/O bumps, wherein the first die and the second die are electrically connected through a second circuit extending between the first die and the second die.
15. The IC chip of claim 14 , wherein the second die includes at least one of pipelining circuits or control circuits for the driver circuits of the first die.
16. The IC chip of claim 14 , wherein the first die is stacked vertically with the second die.
17. The IC chip of claim 14 , wherein the first die is positioned adjacent to the second die along a lateral direction.
18. The IC chip of claim 14 , further comprising at least one of:
a first shoulder structure abutting the first die along a lateral direction, wherein electrical conduction paths within the first shoulder structure are connected to the first circuit; or
a second shoulder structure abutting the second die along the lateral direction, wherein electrical conduction paths within the second shoulder structure are connected to the second circuit.
19. The IC chip of claim 18 , further comprising:
one or more fan-out circuits adjacent to the LED devices, each fan-out circuit being configured as a redistribution layer (RDL) that is electrically connected to one end of the electrical conduction paths within the first shoulder structure or electrically connected to one end of the electrical conduction paths within the second shoulder structure.
20. The IC chip of claim 19 , wherein the one or more fan-out circuits include a fan-out circuit that is part of the second circuit.