Systems and methods for phase-voltage based motor period measurement and controlled signal path fault detection
A method for phase-voltage based motor period measurement includes generating a commanded phase voltage and applying the commanded phase voltage to a first phase voltage input of an electric motor, a second phase voltage input of the electric motor, and a third phase voltage input of the electric motor, measuring a first period of a phase voltage associated with the first phase voltage input and the second phase voltage input and comparing the measured first period to a frequency of the commanded phase voltage, and, in response to a determination that the measured first period of the phase voltage associated with the first phase voltage input and the second phase voltage input is outside of a range of the frequency associated with the commanded phase voltage, identifying a fault associated with the first integrated circuit or signal path.
1. A method for phase-voltage based motor period measurement, the method comprising:
generating a commanded phase voltage;
applying the commanded phase voltage to a first phase voltage input of an electric motor, a second phase voltage input of the electric motor, and a third phase voltage input of the electric motor, the first phase voltage input and the second phase voltage input being connected to a first differential capacitively coupled interface of a first integrated circuit and the second phase voltage input and the third phase voltage input being connected to a second differential capacitively coupled interface of a second integrated circuit;
measuring, at an integrated analog comparator of the first integrated circuit, a first period of a phase voltage associated with the first phase voltage input and the second phase voltage input;
comparing the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to a frequency associated with the commanded phase voltage; and
in response to a determination that the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input is outside of a range of the frequency associated with the commanded phase voltage, identifying a fault associated with the at least one of the first integrated circuit and a corresponding signal path.
2. The method of claim 1 , further comprising:
measuring, at an integrated analog comparator of the second integrated circuit, a second period of a phase voltage associated with the second phase voltage input and the third phase voltage input;
comparing the second period of the phase voltage associated with the second phase voltage input and the third phase voltage input to the frequency associated with the commanded phase voltage; and
in response to a determination that the second period of the phase voltage associated with the second phase voltage input and the third phase voltage input is outside of a range of the frequency associated with the commanded phase voltage, identifying a fault associated with at least one of the second integrated circuit and a corresponding signal path.
3. The method of claim 1 , wherein the first differential capacitively coupled interface is biased to a mid-supply, and wherein the first differential capacitively coupled interface is configured to provide a differential phase voltage input signal, based on the first phase voltage input and the second phase voltage input, to the first integrated circuit.
4. The method of claim 3 , wherein the first differential capacitively coupled interface is further configured to:
reject high frequency interconnect transients; and
reject high voltage to low voltage domain ground disturbances.
5. The method of claim 1 , wherein the second differential capacitively coupled interface is biased to a mid-supply, and wherein the second differential capacitively coupled interface is configured to provide a differential phase voltage input signal, based on the second phase voltage input and third voltage input, to the second integrated circuit.
6. The method of claim 5 , wherein the second differential capacitively coupled interface is further configured to:
reject high frequency interconnect transients; and
reject high voltage to low voltage domain ground disturbances.
7. The method of claim 1 , wherein the electric motor is associated with a vehicle.
8. The method of claim 1 , wherein generating the commanded phase voltage includes generating the commanded phase voltage during a command of a self-test operation.
9. The method of claim 1 , wherein the commanded phase voltage includes a three phase short upper and a three phase short lower pattern.
10. The method of claim 1 , wherein the first integrated circuit includes a first application specific integrated circuit and wherein the second integrated circuit includes a second application specific integrated circuit.
11. A system for phase-voltage based motor period measurement, the system comprising:
a processor; and
a memory including instructions that, when executed by the processor, cause the processor to:
generate a commanded phase voltage;
apply the commanded phase voltage to a first phase voltage input of an electric motor, a second phase voltage input of the electric motor, and a third phase voltage input of the electric motor, the first phase voltage input and the second phase voltage input being connected to a first differential capacitively coupled interface of a first integrated circuit and the second phase voltage input and the third phase voltage input being connected to a second differential capacitively coupled interface of a second integrated circuit;
measure, at an integrated analog comparator of the first integrated circuit, a first period of a phase voltage associated with the first phase voltage input and the second phase voltage input;
compare the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to a frequency associated with the commanded phase voltage; and
in response to a determination that the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input is outside of a range of the frequency associated with the commanded phase voltage, identify a fault associated with at least one of the first integrated circuit and a corresponding signal path.
12. The system of claim 11 , wherein the instructions further cause the processor to:
measure, at an integrated analog comparator of the second integrated circuit, a second period of a phase voltage associated with the second phase voltage input and the third phase voltage input;
compare the second period of the phase voltage associated with the second phase voltage input and the third phase voltage input to the frequency associated with the commanded phase voltage; and
in response to a determination that the second period of the phase voltage associated with the second phase voltage input and the third phase voltage input is outside of a range of the frequency associated with the commanded phase voltage, identify a fault associated with at least one of the second integrated circuit and a corresponding signal path.
13. The system of claim 11 , wherein the first differential capacitively coupled interface is biased to a mid-supply, and wherein the first differential capacitively coupled interface is configured to provide a differential phase voltage input signal, based on the first phase voltage input and the second phase voltage input, to the first integrated circuit.
14. The system of claim 13 , wherein the first differential capacitively coupled interface is further configured to:
reject high frequency interconnect transients; and
reject high voltage to low voltage domain ground disturbances.
15. The system of claim 11 , wherein the second differential capacitively coupled interface is biased to a mid-supply, and wherein the second differential capacitively coupled interface is configured to provide a differential phase voltage input signal, based on the second phase voltage input and third voltage input, to the second integrated circuit.
16. The system of claim 15 , wherein the second differential capacitively coupled interface is further configured to:
reject high frequency interconnect transients; and
reject high voltage to low voltage domain ground disturbances.
17. The system of claim 11 , wherein the electric motor is associated with a vehicle.
18. The system of claim 11 , wherein the instructions further cause the processor to generate the commanded phase voltage during a command of a self-test operation.
19. The system of claim 11 , wherein the commanded phase voltage includes a three phase short upper and a three phase short lower pattern.
20. An apparatus for phase-voltage based motor period measurement, the apparatus comprising:
a processor; and
a memory including instructions that, when executed by the processor, cause the processor to:
generate, during a command of a self-test operation, a commanded phase voltage;
apply the commanded phase voltage to a first phase voltage input of an electric motor, a second phase voltage input of the electric motor, and a third phase voltage input of the electric motor, the first phase voltage input and the second phase voltage input being connected to a first differential capacitively coupled interface of a first integrated circuit and the second phase voltage input and the third phase voltage input being connected to a second differential capacitively coupled interface of a second integrated circuit;
measure, at an integrated analog comparator of the first integrated circuit, a first period of a phase voltage associated with the first phase voltage input and the second phase voltage input;
compare the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input to a frequency associated with the commanded phase voltage;
in response to a determination that the first period of the phase voltage associated with the first phase voltage input and the second phase voltage input is outside of a range of the frequency associated with the commanded phase voltage, identify a fault associated with at least one of the first integrated circuit and a corresponding signal path;
measure, at an integrated analog comparator of the second integrated circuit, a second period of a phase voltage associated with the second phase voltage input and the third phase voltage input;
compare the second period of the phase voltage associated with the second phase voltage input and the third phase voltage input to the frequency associated with the commanded phase voltage; and
in response to a determination that the second period of the phase voltage associated with the second phase voltage input and the third phase voltage input is outside of a range of the frequency associated with the commanded phase voltage, identify a fault associated with at least one of the second integrated circuit and a corresponding signal path.