Systems and methods for fabrication of superconducting integrated circuits
Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.
1. An integrated circuit structure, comprising:
a first wiring layer that comprises an electrically conductive material and which resides in a first plane, the first wiring layer comprising a first mark, the first mark having a first set of nominal dimensions and a first resistance specified at least in part by the first set of nominal dimensions;
a second wiring layer that comprises an electrically conductive material and which resides in a second plane which at least partially overlies the first plane, the second wiring layer comprising a second mark, the second mark having second set of nominal dimensions and a second resistance specified at least in part by the second set of nominal dimensions, the second mark having a nominal position along at least one coordinate axis with respect to the first mark; and
a first stud via that comprises an electrically conductive material and which resides in between the first and the second planes, the first stud via having a third set of nominal dimensions and a third resistance specified at least in part by the third set of nominal dimensions, the first stud via which provides a signal path between the first mark and the second mark, the second mark which overlaps the stud via in a first resistive overlap region defined by an orthogonal projection of the second mark on the stud via, the first resistance overlap region having a resistance that is larger than a cumulative resistance of the first mark, the second mark and the stud via at least at temperatures above a critical temperature.
2. The integrated circuit structure of claim 1 wherein the first resistance overlap region has a resistance that is at least an order of magnitude larger than a cumulative resistance of the first mark, the second mark and the stud via at least at temperatures above the critical temperature.
3. The integrated circuit structure of claim 1 wherein the stud via comprises a material that is superconductive at least below a critical temperature, the stud via which provides a superconductive signal path between the first mark and the second mark.
4. The integrated circuit structure of claim 1 wherein the stud via comprises niobium.
5. The integrated circuit structure of claim 1 wherein the first wiring layer comprises at least one of niobium and aluminum.
6. The integrated circuit structure of claim 1 wherein the second wiring layer comprises at least one of niobium and aluminum.
7. The integrated circuit structure of claim 1 , further comprising:
a first pair of leads electrically coupled to the first mark; and
a second pair of leads electrically coupled to the second mark, where the first and the second pair of leads allow a Wheatstone bridge circuit to be electrically coupled to the first and the second marks to determine an amount of offset, if any, of the second mark from the nominal position along at least one coordinate axis with respect to the first mark.
8. The integrated circuit structure of claim 1 wherein the first mark has a first width W 1 , a first length which includes a portion L 1 that does not overlap the stud via and a portion L 2 that does overlap the stud via and a first thickness t wire1 , the second mark has a second width W 2 , second length which includes a portion L 2 that does not overlap the stud via and a portion d that does overlap the stud via, and second thickness t wire2 , the stud via has a third width W 3 and a third length L 3 , and the second mark is laterally offset from the first mark by a distance ε along at least one coordinate axis.
9. The integrated circuit structure of claim 1 wherein the first mark, the second mark and the stud via form a first vernier.
10. The integrated circuit structure of claim 9 wherein the first wiring layer comprises a plurality of additional marks, the additional marks of the first wiring layer having a first set of nominal dimensions and a first resistance specified at least in part by the first set of nominal dimensions of the first mark, the second wiring layer comprises a plurality of additional marks, the additional marks of the second wiring layer having a second set of nominal dimensions and a second resistance specified at least in part by the first set of nominal dimensions of the second mark, the integrated circuit structure further comprising a plurality of additional stud vias that electrically couple respective ones of the additional marks of the second wiring layer with respective ones of the additional marks of the first wiring layer, to form a set of respective additional verniers.
11. The integrated circuit structure of claim 10 wherein the first vernier and the set of additional verniers are electrically coupled as a chain of verniers.
12. The integrated circuit structure of claim 11 wherein the chain of verniers includes from 1,000 to 3,200 verniers electrically coupled together in series.
13. A method for fabricating a superconducting integrated circuit, the method comprising:
determining a target resolution of interlayer misalignment to be electrically detectable in the superconducting integrated circuit via a measurement of resistance of portions of the superconducting integrated circuit;
determining a set of dimensions for each of a number of verniers to be formed in the superconducting integrated circuit based at least in part on the determined target resolution of interlayer misalignment to be electrically detectable in the superconducting integrated circuit via a measurement of resistance of portions of the superconducting integrated circuit;
fabricating the superconducting integrated circuit; and
measuring a resistance of portions of the fabricated superconducting integrated circuit.
14. The method of claim 13 wherein determining a set of dimensions for each of a number of verniers to be formed in the superconducting integrated circuit based at least in part on the determined target resolution of interlayer misalignment to be electrically detectable in the superconducting integrated circuit via a measurement of resistance of portions of the superconducting integrated circuit includes: determining a length, a width and a thickness of a first mark in a first wiring layer, determining a length, a width and a thickness of a second mark in a second wiring layer, determining a length, a width and a thickness of a stud via that electrically couples the first and the second marks, and determining a length and a width a first resistive overlap region defined by an orthogonal projection of the second mark on the stud via, such that the first resistance overlap region has a resistance that is larger than a cumulative resistance of the first mark, the second mark and the stud via at least at temperatures above a critical temperature.
15. The method of claim 13 , further comprising:
prior to fabricating the superconducting integrated circuit, determining a total number of the verniers to be formed in the superconducting integrated circuit based at least in part on the determined target resolution of interlayer misalignment to be electrically detectable in the superconducting integrated circuit via a measurement of resistance of portions of the superconducting integrated circuit.
16. The method of claim 13 , further comprising:
prior to fabricating the superconducting integrated circuit, determining a total number of the verniers in each of a plurality of chains of verniers to be formed in the superconducting integrated circuit based at least in part on the determined target resolution of interlayer misalignment to be electrically detectable in the superconducting integrated circuit via a measurement of resistance of portions of the superconducting integrated circuit.
17. The method of claim 13 , further comprising:
determining an amount of interlayer offset along at least one coordinate axis based at least in part of the measured resistance of the portions of the fabricated superconducting integrated circuit.
18. The method of claim 17 , further comprising:
determining whether the determined amount of interlayer offset along at least one coordinate axis is within a threshold tolerance; and
destroying the fabricated superconducting integrated circuit in response to determining that the determined amount of interlayer offset along at least one coordinate axis is not within the threshold tolerance.
19. The method of claim 13 wherein measuring a resistance of portions of the fabricated superconducting integrated circuit includes measuring a resistance of chains of verniers of the fabricated superconducting integrated circuit.
20. The method of claim 13 wherein measuring a resistance of portions of the fabricated superconducting integrated circuit includes measuring a resistance of chains of verniers of the fabricated superconducting integrated circuit via a probe card and at least one Wheatstone bridge circuit.