Current mode logic driver and transmission driver including the same
A transmission driver includes a pulse generator and a current mode logic driver. The pulse generator is configured to generate and output a first pulse signal by synchronizing at a falling edge time point of a first input signal, and generate and output a second pulse signal by synchronizing at a falling edge time point of a second input signal. The current mode logic driver is configured to output a pre-emphasis signal to which pre-emphasis technique has been applied by changing a first load resistance value and a second load resistance value based on the first pulse signal and the second pulse signal, respectively.
1. A transmission driver, comprising:
a current mode logic driver configured to output a pre-emphasis signal to which pre-emphasis technique has been applied by changing a first load resistance value and a second load resistance value based on a first pulse signal and a second pulse signal, respectively; and
a phase inverter configured to receive an input signal and output a first input signal and a second input signal generated by inverting a phase of the first input signal to the current mode logic driver,
wherein a falling edge of the first pulse signal is synchronized with a falling edge of the first input signal, and a falling edge of the second pulse signal is synchronized with a falling edge of the second input signal, and
wherein the current mode logic driver comprises:
a first NMOS transistor configured to receive the first input signal at a gate terminal, and connected between a first output node and a common node;
a second NMOS transistor configured to receive the second input signal at a gate terminal, and connected between a second output node and the common node; and
a third NMOS transistor connected in series with the first and second NMOS transistors.
2. The transmission driver of claim 1 , wherein the phase inverter comprises:
a first OP amp configured to generate the first input signal by buffering the input signal; and
an inverting amplifier, comprising two resistors and a second OP amp, configured to generate the second input signal by inverting the phase of the first input signal.
3. The transmission driver of claim 1 , wherein the third NMOS transistor is turned on according to a bias control signal to flow a bias current activating the current mode logic driver.
4. The transmission driver of claim 3 , wherein the current mode logic driver comprises:
a first load controller, connected between the first output node and a power supply voltage, controlling the first load resistance value by receiving the first pulse signal; and
a second load controller, connected between the second output node and the power supply voltage, controlling the second load resistance value by receiving the second pulse signal.
5. The transmission driver of claim 4 , wherein the first load controller comprises:
a first resistor having an end connected to the power supply voltage and another end connected to the first output node;
a first variable resistor having an end connected to the power supply voltage; and
a first PMOS transistor connecting the first pulse signal to the gate terminal, a source terminal to another end of the first variable resistor, and a drain terminal to the first output node.
6. The transmission driver of claim 5 , wherein the second load controller comprises:
a second resistor having an end connected to the power supply voltage and another end connected to the second output node;
a second variable resistor having an end connected to the power supply voltage; and
a second PMOS transistor connecting the second pulse signal to the gate terminal, the source terminal to another end of the second variable resistor, and the drain terminal to the second output node.
7. The transmission driver of claim 6 , wherein the current mode logic driver further comprises third resistors connected between the first output node and the second output node.
8. The transmission driver of claim 7 , wherein the first pulse signal generated in synchronization with the falling edge time point of the first input signal has a low level first section, and
wherein the second pulse signal generated in synchronization with the falling edge time point of the second input signal has a low level second section.
9. The transmission driver of claim 8 , wherein, in the first section, the first NMOS transistor and the second PMOS transistor are turned off in the first section, and the second NMOS transistor and the first PMOS transistor are turned on.
10. The transmission driver of claim 9 , wherein, in the second section, the first NMOS transistor and the second PMOS transistor are turned on, and the second NMOS transistor and the first PMOS transistor are turned off.
11. The transmission driver of claim 10 , wherein, in the first and second sections, the pre-emphasis signal is output by controlling the first and second load resistance values of the current mode logic driver.
12. A transmission driver, comprising:
a current mode logic driver, comprising:
a first load controller, controlled by a first pulse signal, and connected to a power supply voltage;
a second load controller, controlled by a second pulse signal, and connected to the power supply voltage; and
a phase inverter configured to receive an input signal and output a first input signal and a second input signal generated by inverting a phase of the first input signal to the current mode logic driver,
wherein a falling edge of the first pulse signal is synchronized with a falling edge of the first input signal, and a falling edge of the second pulse signal is synchronized with a falling edge of the second input signal, and
wherein the current mode logic driver comprises:
a first NMOS transistor configured to receive the first input signal at a gate terminal, and connected between a first output node and a common node;
a second NMOS transistor configured to receive the second input signal at a gate terminal, and connected between a second output node and the common node; and
a third NMOS transistor connected in series with the first and second NMOS transistors.
13. The transmission driver of claim 12 , wherein the first NMOS transistor is connected in series with the first load controller, the second NMOS transistor is connected in series with the second load controller, and the third NMOS transistor is connected in series with the first and second NMOS transistors.
14. The transmission driver of claim 12 , wherein the current mode logic driver is configured to output a pre-emphasis signal to which pre-emphasis technique has been applied by changing a first load resistance value and a second load resistance value based on the first pulse signal and the second pulse signal, respectively.
15. The transmission driver of claim 12 , wherein the phase inverter comprises:
a first OP amp configured to generate the first input signal by buffering the input signal; and
an inverting amplifier, comprising two resistors and a second OP amp, configured to generate the second input signal by inverting the phase of the first input signal.
16. The transmission driver of claim 12 , wherein the first input signal and the second input signal have different levels.
17. The transmission driver of claim 12 , wherein the third NMOS transistor is turned on according to a bias control signal to flow a bias current.
18. The transmission driver of claim 12 , wherein the first load controller comprises:
a first resistor having an end connected to the power supply voltage and another end connected to a first output node;
a first variable resistor having an end connected to the power supply voltage; and
a first PMOS transistor connecting the first pulse signal to a gate terminal, a source terminal to another end of the first variable resistor, and a drain terminal to the first output node.
19. The transmission driver of claim 18 , wherein the second load controller comprises:
a second resistor having an end connected to the power supply voltage and another end connected to a second output node;
a second variable resistor having an end connected to the power supply voltage; and
a second PMOS transistor connecting the second pulse signal to the gate terminal, the source terminal to another end of the second variable resistor, and the drain terminal to the second output node.