SUPERCONDUCTING TUNABLE INDUCTANCE
A superconducting integrated circuit is fabricated by depositing a ground plane to at least partially overlie a substrate, depositing an insulating layer to at least partially overlie the ground plane, depositing a superconducting layer to at least partially overlie the insulating layer, and forming a superconducting feature in the superconducting layer. An inductance of the superconducting feature is tunable by adjusting a bias current in the ground plane. The ground plane is electrically communicatively coupleable to an electrical ground. Depositing a ground plane includes depositing a first superconducting material to at least partially overlie the substrate and depositing a second superconducting material to at least partially overlie the first superconducting material. A second critical current density of the second superconducting material is higher than a first critical current density of the first superconducting material.
1 . A method of fabricating a superconducting integrated circuit, the method comprising:
depositing a ground plane to at least partially overlie a substrate, the ground plane which is electrically communicatively coupleable to an electrical ground;
depositing an insulating layer to at least partially overlie the ground plane;
depositing a superconducting layer to at least partially overlie the insulating layer;
forming a superconducting feature in the superconducting layer, wherein an inductance of the superconducting feature is tunable by adjusting a bias current in the ground plane, and wherein the depositing a ground plane includes depositing a first superconducting material to at least partially overlie the substrate and depositing a second superconducting material to at least partially overlie the first superconducting material, a second critical current density of the second superconducting material which is higher than a first critical current density of the first superconducting material.
2 . The method of claim 1 wherein the depositing a ground plane to at least partially overlie a substrate includes depositing the ground plane to at least partially overlie a silicon substrate.
3 . The method of claim 1 wherein the depositing an insulating layer to at least partially overlie the ground plane includes planarizing the insulating layer.
4 . The method of claim 1 wherein the depositing an insulating layer to at least partially overlie the ground plane includes depositing a low-loss dielectric.
5 . The method of claim 4 wherein the depositing a low-loss dielectric includes depositing silicon dioxide.
6 . The method of claim 1 wherein the depositing a superconducting layer to at least partially overlie the insulating layer includes depositing at least one of niobium or aluminum.
7 . The method of claim 1 wherein the forming a superconducting feature in the superconducting layer includes patterning the superconducting layer by at least one masking and at least one etching.
8 . The method of claim 1 wherein the depositing a first superconducting material includes depositing at least one of titanium nitride or niobium nitride.
9 . The method of claim 1 wherein the depositing a second superconducting material to at least partially overlie the first superconducting material includes depositing at least one of niobium or aluminum.
10 . The method of claim 1 wherein the depositing a second superconducting material to at least partially overlie the first superconducting material, a second critical current density of the second superconducting material which is higher than a first critical current density of the first superconducting material includes depositing the second superconducting material to at least partially overlie the first superconducting material, the second critical current density of the second superconducting material which is greater than 2×10 −3 amperes.
11 . A tunable inductance comprising:
a substrate:
a ground plane at least partially overlying the substrate, the ground plane comprising a first layer of a first superconducting material at least partially overlying the substrate and a second layer of a second superconducting material, the second layer at least partially overlying the first layer, the ground plane which is electrically communicatively coupleable to an electrical ground;
an insulating layer at least partially overlying the ground plane;
a superconducting layer at least partially overlying the insulating layer; and
a superconducting inductance formed in the superconducting layer;
wherein a second critical current density of the second superconducting material is higher than a first critical current density of the first superconducting material.
12 . The tunable inductance of claim 11 wherein the substrate includes a silicon substrate.
13 . The tunable inductance of claim 11 wherein the insulating layer includes a planarized insulating layer.
14 . The tunable inductance of claim 11 wherein the insulating layer includes a low-loss dielectric.
15 . The tunable inductance of claim 14 wherein the low-loss dielectric includes silicon dioxide.
16 . The tunable inductance of claim 11 wherein the superconducting layer includes at least one of niobium or aluminum.
17 . The tunable inductance of claim 11 wherein the superconducting inductance includes a pattern, the pattern which includes at least one feature selected from the group consisting of a straight line, a spiral, and a meander.
18 . The tunable inductance of claim 11 wherein the first superconducting material includes at least one of titanium nitride or niobium nitride.
19 . The tunable inductance of claim 11 wherein the second superconducting material includes at least one of niobium or aluminum.
20 . The tunable inductance of claim 11 wherein the second critical current density of the second superconducting material is greater than 2×10 −3 amperes.