Target ranging with subsampled noise correlation
View Patent ↗Backend components for noise radar and techniques for operation of those components are provided. Some embodiments include noise radar apparatuses. A noise radar apparatus may include a first unit that generates a random signal or a broadband noise signal using asynchronous logic gates constituting the first unit. The noise radar apparatus also may include a second unit that generates a reference sequence using the generated random signal or the generated broadband noise signal. The second unit comprises at least one tapped delay line formed by second asynchronous logic gates having sampling functionality and storage functionality. The noise radar apparatus may further include a third unit that receives a return signal correlates the return signal and the reference sequence in nearly real-time using third asynchronous logic gates constituting the third unit.
1. A radar comprising:
storage circuitry comprising a first tap, wherein the storage circuitry is configured to transmit a first signal comprising switching frequencies defining digital transitions of the first signal, wherein the switching frequencies comprise a maximum switching frequency, wherein the maximum switching frequency comprises a shortest mean period between the digital transitions of the first signal with respect to the switching frequencies, and wherein the first signal has a power spectral density that is substantially constant over a bandwidth of 20 KHz; and
a register configured to receive the first signal according to the first tap, and store a representation of the first signal according to a clock signal having a clock frequency less than the maximum switching frequency.
2. The radar of claim 1 , wherein the storage circuitry further comprises a second tap and a transmission delay circuit comprising a first delay element, a second delay element, and a third delay element, wherein the first delay element is spaced from the second delay element a first transmission distance with the first tap there between and the second delay element is spaced from the third delay element a second transmission distance with the second tap there between, wherein the storage circuitry is arranged such that the first signal traverses the first delay element before the second delay element.
3. The radar of claim 2 , wherein the transmission delay circuit comprises an even quantity of delay elements, wherein the delay elements comprise the first delay element, the second delay element, and the third delay element, and wherein the delay elements are inverters.
4. The radar of claim 2 , further comprising:
correlator circuitry comprising a correlator tap, wherein the correlator circuitry is configured to receive a second signal reflected from a target; and
an exclusive NOR gate configured to receive the correlator tap and the representation.
5. The radar of claim 4 , wherein the correlator circuitry comprises a second correlator tap and a reception delay circuit comprising a third correlator delay element, a second correlator delay element, and a first correlator delay element, wherein:
the third correlator delay element is spaced the first transmission distance from the second correlator delay element with the second correlator tap there between,
the second correlator delay element is spaced the second transmission distance from the first correlator delay element with the correlator tap there between, and
the correlator circuitry arranged such that the second signal traverses the third correlator delay element before the second correlator delay element.
6. The radar of claim 5 , wherein the correlator circuitry comprises an accumulator configured to transmit an indication that the second signal is based on the first signal transmitted from the radar.
7. The radar of claim 1 , further comprising:
a first bistable circuit comprising a first clock input, a first delay input, a first bistable output, and a first inverted output, wherein the first clock input is configured to receive a second signal, the first delay input is configured to receive the first inverted output, and the first bistable output is configured to output the first signal, wherein the digital transitions of the first signal are fewer than digital transitions of the second signal over a duration.
8. The radar of claim 7 , further comprising:
a second bistable circuit comprising a second clock input, a second delay input, a second bistable output, and a second inverted output, wherein the second clock input is configured to receive a third signal, the second delay input is configured to receive the second inverted output, and the second bistable output is configured to output the first signal, wherein the digital transitions of the second signal are fewer than digital transitions of the third signal.
9. The radar of claim 1 , further comprising:
a logic gate configured to receive an input and an output operable to define a second signal based on the input, wherein the logic gate comprises an exclusive OR circuitry; and
delay circuitry comprising an inverter, wherein the delay circuitry is configured to receive the second signal and define the input according to the inverter, wherein the first signal is based on the second signal.
10. The radar of claim 1 , wherein the first signal is substantially binary comprising an ON voltage and an OFF voltage, and wherein digital transitions between the ON voltage and the OFF voltage define periods that are unique over 8,000 nanoseconds.
11. The radar of claim 1 , wherein a minimum power of the power spectral density over a 50 MHz band is within 10 dB of a maximum power of the power spectral density over the 50 MHz band.
12. A method comprising:
generating a first signal comprising switching frequencies defining digital transitions of the first signal, wherein the switching frequencies comprise a maximum switching frequency, wherein the maximum switching frequency comprises a shortest mean period between the digital transitions of the first signal with respect to the switching frequencies, and wherein the first signal has a power spectral density that is substantially constant over a bandwidth of 20 KHz; and
tapping the first signal to store contemporaneous values of the first signal in registers according to a clock signal, wherein the clock signal comprises a clock frequency less than the maximum switching frequency.
13. The method of claim 12 , further comprising:
receiving a second signal based on the first signal reflected from a target;
receiving the contemporaneous values;
comparing the contemporaneous values with the second signal; and
outputting an indication that the second signal is based on the first signal.
14. A radar comprising:
correlator circuitry comprising a correlator tap, wherein the correlator circuitry is configured to receive a reflected signal based on a first signal reflected from a target, wherein the first signal comprises switching frequencies defining digital transitions of the first signal, wherein the switching frequencies comprise a maximum switching frequency, and wherein the maximum switching frequency comprises a shortest mean period between the digital transitions with respect to the switching frequencies; and
an exclusive NOR gate configured to receive the correlator tap and a binary value based on the first signal.
15. The radar of claim 14 , wherein the binary value is defined by a register configured to receive the first signal, wherein the register is configured to store the first signal according to a clock signal comprising a clock frequency less than the maximum switching frequency.
16. The radar of claim 14 , wherein the correlator circuitry comprises a second correlator tap and a reception delay circuit comprising a third correlator delay element, a second correlator delay element, and a first correlator delay element, wherein the third correlator delay element is spaced from the second correlator delay element a first transmission distance with the second correlator tap there between and the second correlator delay element is spaced from the first correlator delay element a second transmission distance with the correlator tap there between.
17. The radar of claim 16 further comprising:
storage circuitry comprising a first tap, wherein the storage circuitry is configured to transmit the first signal; and
a register configured to receive the first signal according to the first tap, and store the first signal according to a clock signal having a clock frequency less than the maximum switching frequency.
18. The radar of claim 17 , wherein the storage circuitry comprises a second tap and a transmission delay circuit comprising a first delay element, a second delay element, and a third delay element, wherein the first delay element is spaced from the second delay element the first transmission distance with the first tap there between and the second delay element is spaced from the third delay element the second transmission distance with the second tap there between.
19. The radar of claim 18 , wherein the transmission delay circuit comprises an even quantity of delay elements, the delay elements comprising the first delay element, the second delay element, and the third delay element, wherein the delay elements are inverters.
20. The radar of claim 19 , further comprising:
a first bistable circuit comprising a clock input, a delay input, a bistable output, and an inverted output, wherein the clock input is configured to receive a second signal, the delay input is configured to receive the inverted output, and the bistable output is configured to output the first signal, wherein the digital transitions of the first signal are fewer than digital transitions of the second signal over a duration.