Methods for row hammer mitigation and memory devices and systems employing the same
View Patent ↗A method of operating a memory device is provided, comprising determining a number of operations corresponding to a memory location during a first timing period; and scheduling an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold. A memory device is provided, comprising a memory including a memory location; and circuitry configured to: determine a number of operations corresponding to the memory location during a first timing period; and schedule an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold.
1. A method of operating a memory device, comprising:
determining a number of operations corresponding to a memory location during a refresh period; and
scheduling an extra non-periodic refresh operation for the memory location after the refresh period when the determined number of operations exceeds a predetermined threshold.
2. The method of claim 1 , wherein the extra non-periodic refresh operation is scheduled at the completion of the refresh period if a periodic refresh operation is not already scheduled at the completion of the refresh period.
3. The method of claim 1 , wherein the extra non-periodic refresh operation is scheduled at the completion of a second refresh period immediately following the refresh period if a periodic refresh operation is already scheduled at the completion of the refresh period.
4. The method of claim 1 , further comprising:
maintaining a count of refresh operations scheduled for the memory location.
5. The method of claim 4 , wherein maintaining the count comprises determining repeated refresh commands to the same memory location without a corresponding increase in a refresh address counter.
6. The method of claim 1 , wherein the operations comprise activations.
7. The method of claim 1 , wherein the refresh period comprises a base refresh interval.
8. The method of claim 7 , wherein the memory device is configured to be refreshed less often than every base refresh internal.
9. The method of claim 1 , wherein the scheduling the extra non-periodic refresh operation is dependent upon a refresh rate multiplier of the memory device being below a predetermined threshold value.
10. A memory device, comprising:
a memory including a memory location; and
circuitry configured to:
determine a number of operations corresponding to the memory location during a refresh period; and
schedule an extra non-periodic refresh operation for the memory location after the refresh period when the determined number of operations exceeds a predetermined threshold.
11. The memory device of claim 10 , wherein the circuitry is configured to schedule the extra non-periodic refresh operation at the completion of the refresh period if a periodic refresh operation is not already scheduled at the completion of the refresh period.
12. The memory device of claim 10 , wherein the circuitry is configured to schedule the extra non-periodic refresh operation at the completion of a second refresh period immediately following the refresh period if a periodic refresh operation is already scheduled at the completion of the refresh period.
13. The memory device of claim 10 , wherein the circuitry is further configured to maintain a count of refresh operations scheduled for the memory location.
14. The memory device of claim 13 , wherein the circuitry is configured to maintain the count by determining repeated refresh commands to the same memory location without a corresponding increase in a refresh address counter.
15. The memory device of claim 10 , wherein the operations comprise activations.
16. The memory device of claim 10 , wherein the refresh period comprises a base refresh interval.
17. The memory device of claim 16 , wherein the memory device is configured to be refreshed less often than every base refresh interval.
18. The memory device of claim 10 , wherein the circuitry is further configured to maintain the determined number of operations in a counter of the memory device.
19. The memory device of claim 18 , wherein the circuitry is configured to reset the counter upon completion of the refresh period.
20. The memory device of claim 10 , wherein the circuitry is further configured to schedule the extra non-periodic refresh operation for the memory location in response to a determination that a refresh rate multiplier of the memory device is below a predetermined threshold value.
21. A system, comprising:
a memory device including a memory location; and
a memory controller operatively coupled to the memory device and configured to:
determine a number of operations corresponding to the memory location during a refresh period; and
schedule an extra non-periodic refresh operation for the memory location after the refresh period when the determined number of operations exceeds a predetermined threshold.