IP Library Granted Patent US 11,606,313
Granted Patent B2
US 11,606,313 · App. 17/329,214 · Granted Mar 14, 2023

Network switch, non-transitory computer-readable storage medium, and control method

Inventor: Jun Kato (Kawasaki, JP)
Assignee: FUJITSU LIMITED
H04L49/25H04L47/32H04L49/10H04L49/70
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Quick Facts
Patent No.
US 11,606,313
App. No.
17/329,214
Granted
Mar 14, 2023
Kind
B2
Abstract

A network switch includes a field programmable gate array (FPGA) and a processor. The FPGA is configured to transfer a processing target packet to a transfer destination, based on transfer definition information, and to transfer a copy of the processing target packet to the processor. The processor is configured to delete an entry of the transfer definition information based on a transfer record information, and to update the transfer record information based on the copy of the processing target packet.

Claims (32)

1. A network switch comprising:

a processor; and

a field programmable gate array (FPGA) configured to:

determine whether a processing target packet is a specific packet, based on transfer definition information;

transfer, when the processing target packet is the specific packet, a copy of the processing target packet to the processor; and

the processor is configured to:

update transfer record information based on the copy of the processing target packet which is transferred from the FPGA;

delete an entry of the transfer definition information based on the transfer record information which is updated;

cause the FPGA to transfer the copy of the processing target packet, by setting a virtual port to the transfer definition information as a transfer destination of the processing target packet; and

set the virtual port to the transfer definition information as the transfer destination of the processing target packet, when an immediate deletion request for an entry in the transfer definition information is not issued for a transmission source or a destination whose packet non-transfer time is equal to or longer than a threshold value in the transfer record information.

2. The network switch according to claim 1 , wherein the FPGA sets identification information that indicates a fact of being a copy, to the copy of the processing target packet.

3. The network switch according to claim 1 , wherein after the processor updates the transfer record information, the copy of the processing target packet is discarded.

4. The network switch according to claim 1 , wherein the FPGA transfer, both when the processing target packet is not the specific packet and when the processing target packet is the specific packet, the processing target packet to the transfer destination.

5. A non-transitory computer-readable storage medium storing a program that causes a processor included in a network apparatus to execute a process, the process comprising:

determining, by a field programmable gate array (FPGA), whether a processing target packet is a specific packet, based on transfer definition information;

transferring, by the FPGA, when the processing target packet is the specific packet, a copy of the processing target packet to the processor;

updating transfer record information based on a copy of the processing target packet which is transferred by the FPGA which is transferred from the FPGA;

deleting an entry of the transfer definition information based on the transfer record information which is updated; and

setting a virtual port to the transfer definition information as a transfer destination of the processing target packet, and causing to transfer the copy of the processing target packet,

the setting includes setting the virtual port to the transfer definition information as the transfer destination of the processing target packet, when an immediate deletion request for an entry in the transfer definition information is not issued for a transmission source or a destination whose packet non-transfer time is equal to or longer than a threshold value in the transfer record information.

6. The non-transitory computer-readable storage medium according to claim 5 , wherein the process further comprising causing the FPGA to determine the copy of the processing target packet based on identification information indicating a fact of being a copy, the identification information being set the copy of the processing target packet.

7. The network switch according to claim 5 , wherein the process further comprising causing to discard the copy of the processing target packet after the updating.

8. The non-transitory computer-readable storage medium according to claim 5 , wherein the processing target packet is transferred to the transfer destination both when the processing target packet is not the specific packet and when the processing target packet is the specific packet.

9. A control method performing by a network apparatus including a field programmable gate array (FPGA) and a processor, the control method comprising:

determining, by the FPGA, whether a processing target packet is a specific packet, based on transfer definition information;

transferring, by the FPGA, when the processing target packet is the specific packet, a copy of the processing target packet to the processor;

updating, by the processor, transfer record information based on the copy of the processing target packet which is transferred from the FPGA; deleting an entry of the transfer definition information based on the transfer record information which is updated; and

setting, by the processor, a virtual port to the transfer definition information as a transfer destination of the processing target packet, and causing, by the processor, to transfer the copy of the processing target packet,

the setting includes setting the virtual port to the transfer definition information as the transfer destination of the processing target packet, when an immediate deletion request for an entry in the transfer definition information is not issued for a transmission source or a destination whose packet non-transfer time is equal to or longer than a threshold value in the transfer record information.

10. The network switch according to claim 9 , further comprising causing the FPGA to determine the copy of the processing target packet based on identification information indicating a fact of being a copy, the identification information being set the copy of the processing target packet.

11. The network switch according to claim 9 , further comprising causing to discard the copy of the processing target packet after the updating.

12. The network switch according to claim 9 , wherein the processing target packet is transferred to the transfer destination both when the processing target packet is not the specific packet and when the processing target packet is the specific packet.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ORIGINAL COVER SHEET BY REMOVING PATENT NUMBER 10586039 PREVIOUSLY RECORDED ON REEL 69272 FRAME 546. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 1, 2025
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 070764/0091 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2024
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 069272/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2021
From: KATO, JUN
To: FUJITSU LIMITED
Reel/Frame 056366/0571 →
Priority Claims (1)
JP JP2020-132584 · Aug 4, 2020 · national
Continuity (1)
Related Publication 20220045970A1 · Feb 10, 2022