Dynamic division ratio charge pump switching
Circuits and methods to mitigate or eliminate potentially damaging events (e.g., damaging current spikes from in-rush current, charge transfer current, short circuits, etc.) in DC-DC power converters. Embodiments enable dynamic switching of conversion ratios in reconfigurable power converters while under load without turning off the power converter circuitry or suspending switching of the charge pump power switches. Embodiments selectively increase the ON resistance, R ON , for at least some power FETs in a power converter by actively controlling the driver voltage to the gates of the power FETs. During normal operation, the power FET driver voltage may be set to overdrive the FET gate to lower R ON to a desired level that allows high current flow. For other scenarios, the power FET driver voltage may be reduced so as to increase R ON while ON and thus impede current flow to provide protection against potentially damaging events.
1. A gate control circuit for controlling current flow through a power FET having a gate, the gate control circuit including:
(a) a voltage control circuit including a first selectable configuration electrically disconnected from a node, and a second selectable configuration electrically coupled to the node, wherein the node has a first voltage in the first selectable configuration and a lower second voltage in the second selectable configuration; and
(b) a voltage supply device having a gate coupled to the node and a conduction channel configured to be coupled to the gate of the power FET and to provide an output voltage to the gate of the power FET in response to the voltage at the node, wherein an ON resistance, R ON , of the power FET in a first ON state is lowered when the voltage control circuit is in the first selectable configuration during normal operation of the power FET and current flow through the power FET in a second ON state is restricted when the voltage control circuit is in the second selectable configuration.
2. The invention of claim 1 , wherein the gate control circuit is configured to restrict current flow through the power FET in the second ON state upon the occurrence of a potentially damaging event.
3. The invention of claim 2 , wherein the power FET is part of a power converter, and the potentially damaging event results from a dynamic re-configuration of a conversion ratio of the power converter.
4. The invention of claim 2 , wherein the power FET is part of a power converter, and the potentially damaging event results from startup of the power converter.
5. The invention of claim 2 , wherein the power FET is part of a power converter, and the potentially damaging event results from charge re-balancing within the power converter.
6. A gate driver circuit for regulating an ON resistance, R ON , of a power FET in a power converter circuit, the gate driver circuit including:
(a) a current source coupled between a first voltage source and a node;
(b) a voltage regulator coupled to the node and configured to provide a voltage at the node;
(c) a voltage control circuit including a first selectable configuration electrically disconnected from the node, and a second selectable configuration electrically coupled to the node, wherein the voltage at the node when the voltage control circuit is in the first selectable configuration is higher than in the second selectable configuration; and
(d) driving circuitry, coupled between the node and the gate of the power FET, for applying at least two selectable voltages to the gate of the power FET such that the R ON of the power FET is lower when the voltage control circuit is in the first selectable configuration than when the voltage control circuit is in the second selectable configuration.
7. The invention of claim 6 , wherein the voltage control circuit includes:
(a) a switch;
(b) a first diode-connected FET; and
(c) at least one additional diode-connected FET;
wherein the switch, the first diode-connected FET, and the at least one additional diode-connected FET are coupled in series between the node of the gate driver circuit and a reference voltage.
8. The invention of claim 6 , wherein the voltage regulator is a Zener diode.
9. The invention of claim 6 , wherein the driving circuitry includes a plurality of series-coupled inverters coupled to the gate of the power FET.
10. A gate control circuit for a power FET in a power converter circuit, including:
(a) a level shifter including an input configured to receive a control signal and output a voltage-shifted version of the control signal to control the power FET;
(b) a gate driver circuit including:
(1) a current source coupled between a first voltage source and a node;
(2) a voltage regulator coupled to the node and configured to provide a voltage at the node;
(3) a voltage control circuit including a first selectable configuration electrically disconnected from the node, and a second selectable configuration electrically coupled to the node which lowers the voltage at the node; and
(4) a voltage supply circuit element coupled to the node and configured to provide an output voltage in response to the voltage at the node; and
(c) a buffer circuit coupled to the output of the level shifter and to the output voltage from the voltage supply circuit element, the buffer circuit configured to be coupled to a gate of the power FET, wherein the buffer circuit provides a drive voltage to the gate of the power FET having a first voltage when the voltage control circuit is in the first selectable configuration and a second, lower voltage when the voltage control circuit is in the second selectable configuration.
11. The invention of claim 10 , wherein the voltage control circuit includes:
(a) a switch;
(b) a first diode-connected FET; and
(c) at least one additional diode-connected FET;
wherein the switch, the first diode-connected FET, and the at least one additional diode-connected FET are coupled in series between the node of the gate driver circuit and a reference voltage.
12. The invention of claim 10 , wherein the voltage regulator is a Zener diode.
13. The invention of claim 10 , wherein the buffer circuit includes a plurality of series-coupled inverters.