Buses for pattern-recognition processors
Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively.
1. A system, comprising:
a pattern-recognition processor comprising a plurality of memory elements and a detection cell coupled to the plurality of memory elements that when in operation search a data stream received by the pattern-recognition processor according to a search criterion, wherein the pattern-recognition processor is configured to receive a first signal over a bus, wherein the pattern-recognition processor is configured to process the first signal to perform a first function at the pattern-recognition processor identically to a memory processing the first signal when received over the bus to perform the first function at the memory, wherein the pattern-recognition processor comprises an output, wherein the pattern-recognition processor is configured to transmit an output interrupt signal from the output in response to an analysis of the data stream by the pattern-recognition processor satisfying the search criterion by advancing to a last search term of the search criterion and matching it.
2. The system of claim 1 , wherein the pattern-recognition processor is configured to receive a second signal over the bus, wherein the pattern-recognition processor is configured to process the second signal to perform a second function at the pattern-recognition processor differently from the memory processing the second signal when received over the bus to perform a third function at the memory.
3. The system of claim 1 , wherein the pattern-recognition processor is configured to receive a second signal over the bus, wherein the pattern-recognition processor is configured to process the second signal to perform a second function at the pattern-recognition processor identically to the memory processing the second signal when received over the bus to perform the second function at the memory when the pattern-recognition processor operates in a first mode.
4. The system of claim 3 , wherein the pattern-recognition processor is configured to receive the second signal over the bus, wherein the pattern-recognition processor is configured to process the second signal to perform the second function at the pattern-recognition processor differently from the memory processing the second signal when received over the bus to perform a third function at the memory when the pattern-recognition processor operates in a second mode.
5. The system of claim 1 , comprising a CPU coupled to the pattern-recognition processor via the bus.
6. The system of claim 5 , wherein the pattern-recognition processor and the CPU are separate components.
7. The system of claim 5 , wherein the pattern-recognition processor and the CPU are integrated as a single component.
8. The system of claim 5 , wherein the CPU is configured to respond to the output interrupt signal by directing the pattern-recognition processor to enter a search-report mode.
9. The system of claim 1 , comprising a pattern-recognition bus controller coupled to a CPU via a control bus and a data bus and coupled to the pattern-recognition processor via the bus.
10. The system of claim 9 , comprising a memory bus controller coupled to the memory via the bus.
11. The system of claim 10 , wherein the memory bus controller and the pattern-recognition bus controller are separate components.
12. The system of claim 10 , wherein the memory bus controller and the pattern-recognition bus controller are integrated as a single component.
13. The system of claim 10 , wherein the pattern-recognition bus controller is configured to communicate with the pattern-recognition processor through a communication protocol that is at least similar to that used by the memory bus controller.
14. A system, comprising:
a pattern-recognition processor comprising an integrated circuit having a first input pin as an address pin configured to receive a first signal over a bus and a second input pin as a data pin configured to receive a data stream to be searched by the pattern-recognition processor, wherein the pattern-recognition processor is configured to process the first signal as a first type of pattern-recognition processor configuration signal when the pattern-recognition processor is in a first mode of operation, wherein the pattern-recognition processor is configured to process the first signal as a second type of pattern-recognition processor configuration signal when the pattern-recognition processor is in a second mode of operation, wherein the pattern-recognition processor is configured to process the first signal as a third type of pattern-recognition processor configuration signal when the pattern-recognition processor is in a third mode of operation, wherein the pattern-recognition processor is configured to receive the first signal at the address pin separate from a receipt of the data stream to be searched by the pattern-recognition processor at the data pin.
15. The system of claim 14 , wherein the pattern-recognition processor is configured to perform a search of the data stream.
16. The system of claim 15 , wherein the pattern-recognition processor is configured to transmit a search result as a result of the search of the data stream.
17. The system of claim 14 , wherein the pattern-recognition processor is configured to receive a second signal over the bus, wherein the pattern-recognition processor is configured to access a register in response to receipt of the second signal.
18. The system of claim 14 , comprising a CPU coupled to the pattern-recognition processor, wherein the pattern-recognition processor is configured to transmit a second signal over the bus to indicate satisfaction of a search criterion by the pattern-recognition processor.
19. A system, comprising:
a pattern-recognition processor comprising a plurality of memory elements and a detection cell coupled to the plurality of memory elements that when in operation search a data stream received by the pattern-recognition processor according to a search criterion, wherein the pattern-recognition processor is configured to receive a signal over a bus, wherein the pattern-recognition processor is configured to process the signal to perform a first function at the pattern-recognition processor identically to a memory processing the signal when received over the bus to perform the first function at the memory when the pattern-recognition processor operates in a first mode, wherein the pattern-recognition processor is configured to process the signal to perform a second function at the pattern-recognition processor differently from the memory processing the signal when received over the bus to perform a third function at the memory when the pattern-recognition processor operates in a second mode, wherein the pattern-recognition processor comprises a register, wherein the pattern-recognition processor is configured to periodically receive a request to determine whether the pattern-recognition processor has detected a match as a satisfied criterion by advancing to a last search term of the search criterion and matching it when analyzing the data stream, wherein the pattern-recognition processor is configured to store an indication of the match in the register.
20. The system of claim 19 , wherein the bus comprises a same number of connections as a memory bus.