Optimized branching using safe static keys
Systems and methods for managing optimized branching in executable instructions are disclosed. In one implementation, a processing device may identify, in a sequence of executable instructions, a branching instruction associated with a safe static key, the branching instruction specifying a first target location. The processing device may determine whether a value of the safe static key is initialized. Responsive to determining that the value of the safe static key is initialized, the processing device may further replace the branching instruction with an unconditional branching instruction specifying the first target location. Responsive to determining that the value of the safe static key is uninitialized, the processing device may replace the branching instruction with a conditional branching instruction specifying the first target location.
1. A method comprising:
identifying, in a sequence of executable instructions, a branching instruction associated with a safe static key, the branching instruction specifying a first target location;
determining whether a value of the safe static key is initialized;
responsive to determining that the value of the safe static key is initialized, replacing the branching instruction with an unconditional branching instruction specifying the first target location; and
responsive to determining that the value of the safe static key is uninitialized, replacing the branching instruction with a conditional branching instruction specifying the first target location.
2. The method of claim 1 , wherein the safe static key is a part of a conditional expression associated with the branching instruction.
3. The method of claim 1 , wherein the sequence of executable instructions is executed by a process running on a virtual machine.
4. The method of claim 1 , wherein the branching instruction is a jump instruction.
5. The method of claim 1 further comprises:
responsive to determining that a condition is satisfied, replacing the branching instruction with the conditional branching instruction, wherein the condition comprises detecting a boot sequence of a virtual machine executing the sequence of instructions.
6. The method of claim 1 further comprising:
responsive to determining that a rate of modification of the safe static key exceeds a threshold rate, replacing the unconditional branching instruction with the conditional branching instruction specifying the first target location.
7. The method of claim 6 , wherein determining that the rate of modification of the safe static key exceeds the threshold rate further comprises:
detecting that the unconditional branching instruction is modified;
adding a timestamp of a current time to a list of code modification timestamps; and
determining the rate of modification of the unconditional branching instruction as a number of entries in the list of code modification timestamps that fall within a predetermined window.
8. The method of claim 7 further comprising:
responsive to adding the timestamp of the current time to the list of code modification timestamps, deleting an earliest timestamp from the list of code modification timestamps.
9. A system comprising:
a memory; and
a processing device operatively coupled to the memory, wherein the processing device is further to:
identify, in a sequence of executable instructions, a branching instruction associated with a safe static key, the branching instruction specifying a first target location;
determine whether a value of the safe static key is initialized;
responsive to determining that the value of the safe static key is initialized, replace the branching instruction with an unconditional branching instruction specifying the first target location; and
responsive to determining that the value of the safe static key is uninitialized, replace the branching instruction with a conditional branching instruction specifying the first target location.
10. The system of claim 9 , wherein the safe static key is a part of a conditional expression associated with the branching instruction.
11. The system of claim 9 , wherein the processing device is further to:
responsive to determining that a rate of modification of the safe static key exceeds a threshold rate, replace the unconditional branching instruction with the conditional branching instruction specifying the first target location.
12. The system of claim 11 , wherein to determine that the rate of modification of the safe static key exceeds the threshold rate, the processing device is further to:
detect that the unconditional branching instruction is modified;
add a timestamp of a current time to a list of code modification timestamps; and
determine the rate of modification of the unconditional branching instruction as a number of entries in the list of code modification timestamps that fall within a predetermined window.
13. The system of claim 11 , wherein the sequence of executable instructions comprises a compiled program running on a virtual machine.
14. A non-transitory computer-readable storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to:
identify, in a sequence of executable instructions, a branching instruction associated with a safe static key, the branching instruction specifying a first target location;
determine whether a value of the safe static key is initialized;
responsive to determining that the value of the safe static key is initialized, replace the branching instruction with an unconditional branching instruction specifying the first target location; and
responsive to determining that the value of the safe static key is uninitialized, replace the branching instruction with a conditional branching instruction specifying the first target location.
15. The non-transitory computer-readable storage medium of claim 14 , wherein the processing device is further to:
responsive to determining that a rate of modification of the safe static key exceeds a threshold rate, replace the unconditional branching instruction with the conditional branching instruction specifying the first target location.
16. The non-transitory computer-readable storage medium of claim 15 , wherein to determine that the rate of modification of the safe static key exceeds the threshold rate, the processing device is further to:
detect that the unconditional branching instruction is modified;
add a timestamp of a current time to a list of code modification timestamps; and
determine the rate of modification of the unconditional branching instruction as a number of entries in the list of code modification timestamps that fall within a predetermined window.
17. The non-transitory computer-readable storage medium of claim 16 , wherein the processing device is further to:
responsive to adding the timestamp of the current time to the list of code modification timestamps, delete an earliest timestamp from the list of code modification timestamps.
18. The non-transitory computer-readable storage medium of claim 14 , wherein the sequence of executable instructions comprises a compiled program running on a virtual machine.
19. The non-transitory computer-readable storage medium of claim 14 , wherein the processing device is further to:
responsive to determining that a condition is satisfied, replace the branching instruction with the conditional branching instruction, wherein the condition comprises detecting a boot sequence of a virtual machine executing the sequence of instructions.
20. The non-transitory computer-readable storage medium of claim 14 , wherein the branching instruction is a jump instruction.