IP Library Granted Patent US 11,510,317
Granted Patent B1
US 11,510,317 · App. 17/338,369 · Granted Nov 22, 2022

Systems and methods for maximizing signal integrity on circuit boards

Inventors: Sandor Farkas (Round Rock, TX); Bhyrav Mutnury (Austin, TX); Steven Ethridge (Austin, TX)
Assignee: Dell Products L.P.
H05K1/115H05K1/0298H05K3/0047H05K3/4038H05K2201/09545
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Quick Facts
Patent No.
US 11,510,317
App. No.
17/338,369
Granted
Nov 22, 2022
Kind
B1
Abstract

A circuit board may include a plurality of electrically-conductive layers separated and supported by layers of insulating material laminated together and a via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board, the via comprising a first via portion comprising electrically-conductive material and having a first diameter and a first depth from a surface of the circuit board and a second via portion comprising electrically-conductive material and having a second diameter smaller than the first diameter and a second depth from the first depth.

Claims (50)

1. A circuit board, comprising:

a plurality of electrically-conductive layers separated and supported by layers of insulating material laminated together;

a first via having a uniform diameter throughout; and

a second via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board, the second via comprising:

a first via portion comprising electrically-conductive material and having a first diameter and a first depth from a surface of the circuit board; and

a second via portion comprising electrically-conductive material and having a second diameter smaller than the first diameter and a second depth from the first depth; wherein both the first diameter and the second diameter of the second via are smaller than the uniform diameter of the first via.

2. The circuit board of claim 1 , wherein:

the first via portion comprises a first cylindrical tube of the first diameter; and

the second via portion comprises a second cylindrical tube of the second diameter in series with the first via portion.

3. The circuit board of claim 2 , wherein together the first cylindrical tube and the second cylindrical tube form one continuous tube of differing diameters.

4. The circuit board of claim 1 , wherein the first diameter and the second diameter are approximately concentric.

5. The circuit board of claim 1 , wherein the second via comprises a layer of electrically-conductive material formed on interior walls of an opening through the circuit board.

6. The circuit board of claim 1 , wherein a sum of the first depth and the second depth equals a thickness of the circuit board.

7. An information handling system comprising:

an enclosure; and

a circuit board housed in the enclosure, the circuit board comprising:

a plurality of electrically-conductive layers separated and supported by layers of insulating material laminated together;

a first via having a uniform diameter throughout; and

a second via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board, the second via comprising:

a first via portion comprising electrically-conductive material and having a first diameter and a first depth from a surface of the circuit board; and

a second via portion comprising electrically-conductive material and having a second diameter smaller than the first diameter and a second depth from the first depth;

wherein both the first diameter and the second diameter of the second via are smaller than the uniform diameter of the first via.

8. The information handling system of claim 7 , wherein:

the first via portion comprises a first cylindrical tube of the first diameter; and

the second via portion comprises a second cylindrical tube of the second diameter in series with the first via portion.

9. The information handling system of claim 8 , wherein together the first cylindrical tube and the second cylindrical tube form one continuous tube of differing diameters.

10. The information handling system of claim 7 , wherein the first diameter and the second diameter are approximately concentric.

11. The information handling system of claim 7 , wherein the second via comprises a layer of electrically-conductive material formed on interior walls of an opening through the circuit board.

12. The information handling system of claim 7 , wherein a sum of the first depth and the second depth equals a thickness of the circuit board.

13. A method for forming a circuit board, comprising:

forming a plurality of conductive layers separated and supported by layers of insulating material laminated together;

forming a first via between layers of the circuit board; the first via having a uniform diameter throughout; and

forming a second via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board, the second via comprising:

a first via portion comprising electrically-conductive material and having a first diameter and a first depth from a surface of the circuit board; and

a second via portion comprising electrically-conductive material and having a second diameter smaller than the first diameter and a second depth from the first depth;

wherein both the first diameter and the second diameter of the second via are smaller than a diameter of the first via.

14. The method of claim 13 , wherein:

the first via portion comprises a first cylindrical tube of the first diameter; and

the second via portion comprises a second cylindrical tube of the second diameter in series with the first via portion.

15. The method of claim 14 , wherein together the first cylindrical tube and the second cylindrical tube form one continuous tube of differing diameters.

16. The method of claim 13 , wherein the first diameter and the second diameter are approximately concentric.

17. The method of claim 13 , wherein the second via comprises a layer of electrically-conductive material formed on interior walls of an opening through the circuit board.

18. The method of claim 13 , wherein a sum of the first depth and the second depth equals a thickness of the circuit board.

19. The method of claim 13 , wherein forming the second via comprises:

forming a first hole with the first diameter from the surface of the circuit board to the first depth;

forming a second hole with the second diameter from the first depth; and

plating interior surfaces exposed by the hole with electrically-conductive material.

20. The method of claim 13 , wherein:

forming the first hole comprises drilling the first hole with a first drill bit having approximately the first diameter; and

forming the second hole comprises drilling the second hole with a second drill bit having approximately the second diameter.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (058014/0560) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0473 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (057931/0392) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 062022/0382 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (057758/0286) Recorded Jun 10, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
Reel/Frame 061654/0064 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 058014/0560 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 057758/0286 →
SECURITY INTEREST Recorded Oct 6, 2021
From: DELL PRODUCTS L.P.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 057931/0392 →
SECURITY AGREEMENT Recorded Oct 1, 2021
From: DELL PRODUCTS, L.P.; EMC IP HOLDING COMPANY LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
Reel/Frame 057682/0830 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2021
From: FARKAS, SANDOR; MUTNURY, BHYRAV; ETHRIDGE, STEVEN
To: DELL PRODUCTS L.P.
Reel/Frame 056433/0865 →