Fanout processor
Disclosed herein is a processor to process streaming data. The processor includes a TCP client circuit and a TCP server circuit. A fanout circuit is communicatively coupled to the TCP client circuit and the TCP server circuit. The fanout circuit receives data from the TCP client circuit, determines a rate at which to transmit the received market data, and instructs the TCP server circuit to send the received data at the determined rate.
1. A programmable integrated circuit comprising:
a register;
a fanout circuit;
a first transmission control protocol (TCP) client circuit being configured to receive a first stream of market data from a first trade matching engine and provide the first stream of market data to the fanout circuit;
a second TCP client circuit being configured to receive a second stream of market data from a second trade matching engine and provide the second stream of market data to the fanout circuit;
a first TCP server circuit being configured to receive first messages comprising market data from the first stream of market data provided by the first TCP client circuit and second messages comprising market data from the second stream of market data provided by the second TCP client circuit and providing the first messages and the second messages to a first market data gateway; and
a second TCP server circuit being configured to receive the first messages comprising market data from the first stream of market data provided by the first TCP client circuit and the second messages comprising market data from the second stream of market data provided by the second TCP client circuit and providing the first messages and the second messages to a second market data gateway;
wherein the fanout circuit is configured to:
retrieve, from the register, a first number of messages to send per nanosecond to the first market data gateway and a second number of messages to send per nanosecond to the second market data gateway; and
instruct the first TCP server circuit to send the first messages and the second messages at the first number of messages per nanosecond to the first market data gateway; and
instruct the second TCP server circuit to send the first messages and the second messages at the second number of messages per nanosecond to the second market data gateway.
2. The programmable integrated circuit of claim 1 , wherein the first number of messages and the second number of messages are configurable.
3. The programmable integrated circuit of claim 1 , wherein the fanout circuit is further configured to determine a first size of the first messages and a second size of the second messages.
4. The programmable integrated circuit of claim 3 , wherein the first size and the second size are configurable.
5. The programmable integrated circuit of claim 1 , wherein the fanout circuit is communicatively coupled to a fanout controller to receive configurable parameters from the fanout controller.
6. The programmable integrated circuit of claim 5 , wherein the fanout circuit is further configured to:
receive a first predetermined size of a first message and a second predetermined size of a second message from the fanout controller; and
store the first predetermined size and the second predetermined size in the register.
7. The programmable integrated circuit of claim 5 , wherein the fanout circuit is further configured to:
receive the first number of messages per nanosecond and the second number of messages per nanosecond from the fanout controller; and
store the first number of messages per nanosecond and the second number of messages per nanosecond in the register.
8. The programmable integrated circuit of claim 3 , wherein the fanout circuit is further configured to buffer the market data of the first stream until the first size is buffered and providing first messages and buffer the market data of the second stream until the second size is buffered and providing second messages.