Custom baseboard management controller (BMC) firmware stack monitoring system and method
An Information Handling System (IHS) includes multiple hardware devices, and a baseboard Management Controller (BMC) in communication with the plurality of hardware devices. The BMC includes executable instructions for when a custom BMC firmware stack is executed on the BMC, monitoring a parameter of one or more of the hardware devices of the IHS. The instructions that monitor the parameter are separate and distinct from the instructions of the custom BMC firmware stack. The instructions also controls the BMC to perform one or more operations to remediate an excessive parameter when the parameter exceeds a specified threshold.
1. An Information Handling System (IHS), comprising:
a plurality of hardware devices; and
a Baseboard Management Controller (BMC) in communication with the plurality of hardware devices, the BMC comprising:
a system on chip (SoC) device configured to execute first instructions stored in a first memory unit to execute a custom BMC firmware stack; and
a second processor configured to execute second instructions stored in a second memory unit to:
access a secure memory unit in a Basic Input/Output System (BIOS) of the IHS using a secure memory access technique, wherein access to the secure memory unit is only allowed via the secure memory access technique;
wherein the SoC device is restricted from accessing the secure memory unit using the secure memory access technique; and
a third processor configured to execute third instructions stored in a third memory unit to assist the SoC device in performing one or more functions associated with the operation of the BMC, wherein the second instructions are further executed to:
create a memory mapped file in the second memory unit;
copy data stored in the secure memory unit to the memory mapped file;
when the third processor requests at least a portion of the data, send the requested portion of data to the third instructions; and
when the third processor requests to write the portion of data, write the portion of data in the memory mapped file and communicate with the BIOS to update the portion of data in the secure memory unit.
2. The IHS of claim 1 , wherein the second instructions are further executed to send information associated with the memory mapped file to the third processor when the memory mapped file is created, the third processor using the information to request the portion of data.
3. The IHS of claim 1 , wherein the third instructions are further executed to convey the portion of data to a bootloader, the bootloader executed to boot the custom BMC firmware stack.
4. The IHS of claim 1 , wherein the SoC device comprises an advanced RISC machine (ARM) processor, the second processor comprises a coprocessor, and the third processor comprises a complex programmable logic device (CPLD).
5. The IHS of claim 1 , wherein the second instructions are further executed to:
receive a request to read or write at least a portion of the data from the third processor, the request including an identity certificate stored in the third memory;
when the identity certificate is valid, communicate with the BIOS to read or write the portion of data in the secure memory unit according to the received request.
6. The IHS of claim 5 , wherein the BIOS is configured to access the portion of data using a proxy process.
7. The IHS of claim 5 , wherein the second instructions are configured to issue different identity certificates to the third processor at ongoing intervals.
8. A method comprising:
executing, using instructions stored in one or more memory units and executed by one or more processors, a custom BMC firmware stack using a System on Chip (SoC) device configured on a baseboard management controller (BMC); and
using a second processor:
accessing, using the instructions, a secure memory unit in a Basic Input/Output System (BIOS) of an Information Handling System (HIS) using a secure memory access technique, wherein access to the secure memory unit is only allowed via the secure memory access technique;
restricting, using the instructions, access by the SoC device from accessing the secure memory unit using the secure memory access technique;
assisting, by a third processor, the SoC device in performing one or more functions associated with the operation of the BMC, the third processor configured on the system on chip (SoC) device; and
by the second processor:
creating a memory mapped file in the second memory unit;
copying data stored in the secure memory unit to the memory mapped file;
when the third processor request at least a portion of the data, sending the requested portion of data to the third instructions; and
when the third processor requests to write the portion of data, writing the portion of data in the memory mapped file and communicate with the BIOS to update the portion of data in the secure memory unit.
9. The method of claim 8 , further comprising sending, by the second processor, information associated with the memory mapped file to the third processor when the memory mapped file is created, the third processor using the information to request the portion of data.
10. The method of claim 8 , wherein the third instructions are further executed to convey the portion of data to a bootloader, the bootloader executed to boot the custom BMC firmware stack.
11. The method of claim 8 , further comprising by the second processor:
receiving a request to read or write at least a portion of the data from the third processor, the request including an identity certificate stored in the third memory;
when the identity certificate is valid, communicating with the BIOS to read or write the portion of data in the secure memory unit according to the received request.
12. The method of claim 11 , further comprising accessing, by the BIOS, the portion of data using a proxy process.
13. The method of claim 11 , further comprising by the second processor, issuing different identity certificates to the third processor at ongoing intervals.
14. A Baseboard Management Controller (BMC) comprising:
a System on Chip (SoC) device configured to execute first instructions stored in a first memory unit to execute a custom BMC firmware stack, the BMC in communication with the plurality of hardware devices of an Information Handling System (IHS); and
a second processor configured to execute second instructions stored in a second memory unit to:
access a secure memory unit in a Basic Input/Output System (BIOS) of the IHS using a secure memory access technique, wherein access to the secure memory unit is only allowed via the secure memory access technique;
wherein the SoC device is restricted from accessing the secure memory unit using the secure memory access technique; and
a third processor configured to execute third instructions stored in a third memory unit to assist the SoC device in performing one or more functions associated with the operation of the BMC, wherein the second instructions are further executed to:
create a memory mapped file in the second memory unit;
copy data stored in the secure memory unit to the memory mapped file;
when the third processor request at least a portion of the data, send the requested portion of data to the third instructions; and
when the third processor request to write the portion of data, write the portion of data in the memory mapped file and communicate with the BIOS to update the portion of data in the secure memory unit.
15. The BMC of claim 14 , wherein the second instructions are further executed to send information associated with the memory mapped file to the third processor when the memory mapped file is created, the third processor using the information to request the portion of data.
16. The BMC of claim 14 , wherein the third instructions are further executed to convey the portion of data to a bootloader, the bootloader executed to boot the custom BMC firmware stack.
17. The BMC of claim 14 , wherein the SoC device comprises an advanced RISC machine (ARM) processor, the second processor comprises a coprocessor, and the third processor comprises a complex programmable logic device (CPLD).
18. The BMC of claim 14 , wherein the second instructions are further executed to:
receive a request to read or write at least a portion of the data from the third processor, the request including an identity certificate stored in the third memory;
when the identity certificate is valid, communicate with the BIOS to read or write the portion of data in the secure memory unit according to the received request.
19. The BMC of claim 18 , wherein the BIOS is configured to access the portion of data using a proxy process.
20. The BMC of claim 18 , wherein the second instructions are configured to issue different identity certificates to the third processor at ongoing intervals.