Non-disruptive firmware upgrade of asymmetric hardware accelerator systems
In an asymmetric hardware accelerator system, a hardware accelerator configured to handle workloads of a particular type that have a lowest CPU utilization as compared to workloads of other types being handled by other hardware accelerators configured to handle the other types of workloads is identified. A CPU fallback is conducted of workloads of the identified hardware accelerator to the CPU. While the CPU is handling the workloads, firmware of the identified hardware accelerator is upgraded.
1. A method for upgrading firmware of an asymmetric hardware accelerator system coupled to a central processing unit (CPU) comprising:
identifying a hardware accelerator configured to handle workloads of a particular type that have a lowest CPU utilization as compared to workloads of other types being handled by other hardware accelerators configured to handle the other types of workloads;
conducting a CPU fallback of workloads of the identified hardware accelerator to the CPU; and
while the CPU is handling the workloads, upgrading firmware of the identified hardware accelerator, the identified hardware accelerator now being an upgraded hardware accelerator.
2. The method of claim 1 further comprising:
reconfiguring the upgraded hardware accelerator to handle workloads of a type being handled by a next hardware accelerator to upgrade; and
upgrading firmware of the next hardware accelerator while workloads of the type that were being handled by the next hardware accelerator are being handled by the upgraded and reconfigured hardware accelerator.
3. The method of claim 2 further comprising:
repeating the reconfiguring and upgrading until all hardware accelerators have been upgraded;
upon all hardware accelerators having been upgraded, reconfiguring a last upgraded hardware accelerator to handle the workloads of the particular type currently being handled by the CPU, and
offloading the workloads of the particular type from the CPU back to the last upgraded hardware accelerator.
4. The method of claim 1 wherein the hardware accelerators comprise QuickAssist Technology (QAT) compatible accelerators.
5. The method of claim 1 wherein at an initial state of the asymmetric hardware accelerator system before the upgrading of the firmware, each hardware accelerator of the asymmetric hardware accelerator system is configured to handle workloads of a single type.
6. The method of claim 1 further comprising:
during the upgrading the firmware, receiving a request to process a first workload of a first type;
directing the first workload to the CPU;
after the upgrading the firmware, receiving a request to process a second workload of the first type; and
directing the second workload to a last hardware accelerator that was upgraded.
7. A system comprising: a processor; and memory configured to store one or more sequences of instructions which, when executed by the processor, cause the processor to carry out the steps of:
identifying a hardware accelerator configured to handle workloads of a particular type that have a lowest CPU utilization as compared to workloads of other types being handled by other hardware accelerators configured to handle the other types of workloads;
conducting a CPU fallback of workloads of the identified hardware accelerator to a central processing unit (CPU); and
while the CPU is handling the workloads, upgrading firmware of the identified hardware accelerator, the identified hardware accelerator now being an upgraded hardware accelerator.
8. The system of claim 7 wherein the processor further carries out the steps of:
reconfiguring the upgraded hardware accelerator to handle workloads of a type being handled by a next hardware accelerator to upgrade; and
upgrading firmware of the next hardware accelerator while workloads of the type that were being handled by the next hardware accelerator are being handled by the upgraded and reconfigured hardware accelerator.
9. The system of claim 8 wherein the processor further carries out the steps of:
repeating the reconfiguring and upgrading until all hardware accelerators have been upgraded;
upon all hardware accelerators having been upgraded, reconfiguring a last upgraded hardware accelerator to handle the workloads of the particular type currently being handled by the CPU, and
offloading the workloads of the particular type from the CPU back to the last upgraded hardware accelerator.
10. The system of claim 7 wherein the hardware accelerators comprise QuickAssist Technology (QAT) compatible accelerators.
11. The system of claim 7 wherein at an initial state of the asymmetric hardware accelerator system before the upgrading of the firmware, each hardware accelerator of the asymmetric hardware accelerator system is configured to handle workloads of a single type.
12. The system of claim 7 wherein the processor further carries out the steps of:
during the upgrading the firmware, receiving a request to process a first workload of a first type;
directing the first workload to the CPU;
after the upgrading the firmware, receiving a request to process a second workload of the first type; and
directing the second workload to a last hardware accelerator that was upgraded.
13. A computer program product, comprising a non-transitory computer-readable medium having a computer-readable program code embodied therein, the computer-readable program code adapted to be executed by one or more processors to implement a method for upgrading firmware of an asymmetric hardware accelerator system coupled to a central processing unit (CPU), the method comprising:
identifying a hardware accelerator configured to handle workloads of a particular type that have a lowest CPU utilization as compared to workloads of other types being handled by other hardware accelerators configured to handle the other types of workloads;
conducting a CPU fallback of workloads of the identified hardware accelerator to the CPU; and
while the CPU is handling the workloads, upgrading firmware of the identified hardware accelerator, the identified hardware accelerator now being an upgraded hardware accelerator.
14. The computer program product of claim 13 wherein the method further comprises:
reconfiguring the upgraded hardware accelerator to handle workloads of a type being handled by a next hardware accelerator to upgrade; and
upgrading firmware of the next hardware accelerator while workloads of the type that were being handled by the next hardware accelerator are being handled by the upgraded and reconfigured hardware accelerator.
15. The computer program product of claim 14 wherein the method further comprises:
repeating the reconfiguring and upgrading until all hardware accelerators have been upgraded;
upon all hardware accelerators having been upgraded, reconfiguring a last upgraded hardware accelerator to handle the workloads of the particular type currently being handled by the CPU, and
offloading the workloads of the particular type from the CPU back to the last upgraded hardware accelerator.
16. The computer program product of claim 13 wherein the hardware accelerators comprise QuickAssist Technology (QAT) compatible accelerators.
17. The computer program product of claim 13 wherein at an initial state of the asymmetric hardware accelerator system before the upgrading of the firmware, each hardware accelerator of the asymmetric hardware accelerator system is configured to handle workloads of a single type.
18. The computer program product of claim 13 wherein the method further comprises:
during the upgrading the firmware, receiving a request to process a first workload of a first type;
directing the first workload to the CPU;
after the upgrading the firmware, receiving a request to process a second workload of the first type; and
directing the second workload to a last hardware accelerator that was upgraded.