Improving memory access handling for nested virtual machines

1. A method comprising:

running, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine, wherein the Level 2 virtual machine is associated with a Peripheral Component Interconnect (PCI) device;

assigning an input/output (I/O) virtual address space to be used by the PCI device;

receiving, from the Level 1 hypervisor, a guest page table maintained by the Level 1 hypervisor;

generating, by the Level 0 hypervisor, a Level 1 page table by combining records from the guest page table with records from a host page table maintained by the Level 0 hypervisor;

causing a central processing unit (CPU) of the host computer system to use the Level 1 page table for first level address translations;

generating a Level 2 page table comprising a plurality of Level 2 page table entries, wherein each Level 2 page table entry of the plurality of Level 2 page table entries maps a I/O guest virtual address of the I/O virtual address space to a corresponding Level 2 guest physical address; and

causing a device driver of the Level 2 virtual machine to use the Level 2 page table for second level address translation.

2. The method of claim 1 , further comprising:

granting, by the Level 0 hypervisor to the Level 2 virtual machine, direct access to the Level 2 page table.

3. The method of claim 1 , wherein the Level 1 page table comprises a plurality of page table records, wherein each Level 1 page table record of the plurality of Level 1 page table records maps a Level 2 guest physical address of a Level 2 address space associated with the Level 2 virtual machine to a corresponding Level 0 host physical address of a Level 0 address space associated with the Level 0 hypervisor.

4. The method of claim 1 , further comprising:

responsive to removing access, of the PCI device, to a memory page, updating, by the Level 2 virtual machine, a page table entry of the Level 2 page table.

5. The method of claim 1 , further comprising:

receiving a request from the PCI device to access data on a memory page of a plurality of memory pages; and

causing a vCPU of the Level 2 virtual machine to use the Level 2 page table for address translation.

6. The method of claim 1 , wherein the Level 1 page table and the Level 2 page table are part of an input/output memory management unit (IOMMU).

7. The method of claim 1 , further comprising:

granting, by the Level 0 hypervisor to the Level 1 hypervisor, direct access to the Level 1 page table.

8. The method of claim 1 , wherein the I/O virtual address space to be used by the PCI device is assigned by the Level 2 virtual machine.

9. A system, comprising:

a memory;

a processing device operatively coupled to the memory, the processing device configured to:

running a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine, wherein the Level 2 virtual machine is associated with a Peripheral Component Interconnect (PCI) device;

assign an input/output (I/O) virtual address space to be used by the PCI device;

receive, from the Level 1 hypervisor, a guest page table maintained by the Level 1 hypervisor;

generate a Level 1 page table by combining records from the guest page table with records from a host page table maintained by the Level 0 hypervisor;

cause a central processing unit (CPU) of a host computer system to use the Level 1 page table for first level address translations;

generate a Level 2 page table comprising a plurality of Level 2 page table entries, wherein each Level 2 page table entry of the plurality of Level 2 page table entries maps a I/O guest virtual address of the I/O virtual address space to a corresponding Level 2 guest physical address; and

cause a device driver of the Level 2 virtual machine to use the Level 2 page table for second level address translation.

10. The system of claim 9 , further comprising the processing device configured to:

grant, to the Level 2 virtual machine, direct access to the Level 2 page table.

11. The system of claim 9 , wherein the Level 1 page table comprises a plurality of page table records, wherein each Level 1 page table record of the plurality of Level 1 page table records maps a Level 2 guest physical address of a Level 2 address space associated with the Level 2 virtual machine to a corresponding Level 0 host physical address of a Level 0 address space associated with the Level 0 hypervisor.

12. The system of claim 9 , further comprising the processing device configured to:

responsive to removing access, of the PCI device, to a memory page, update, by the Level 2 virtual machine, a page table entry of the Level 2 page table.

13. The system of claim 9 , further comprising the processing device configured to:

receive a request from the PCI device to access data on a memory page of a plurality of memory pages; and

cause a vCPU of the Level 2 virtual machine to use the Level 2 page table for address translation.

14. The system of claim 9 , wherein the Level 1 page table and the Level 2 page table are part of an input/output memory management unit (IOMMU).

15. The system of claim 9 , further comprising the processing device configured to:

granting, by the Level 0 hypervisor to the Level 1 hypervisor, direct access to the Level 1 page table.

16. The system of claim 9 , wherein the I/O virtual address space to be used by the PCI device is assigned by the Level 2 virtual machine.

17. A non-transitory machine-readable storage medium storing instructions that cause a processing device to:

running a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine, wherein the Level 2 virtual machine is associated with a Peripheral Component Interconnect (PCI) device;

assign an input/output (I/O) virtual address space to be used by the PCI device;

receive, from the Level 1 hypervisor, a guest page table maintained by the Level 1 hypervisor;

generate a Level 1 page table by combining records from the guest page table with records from a host page table maintained by the Level 0 hypervisor;

cause a central processing unit (CPU) of a host computer system to use the Level 1 page table for first level address translations;

generate a Level 2 page table comprising a plurality of Level 2 page table entries, wherein each Level 2 page table entry of the plurality of Level 2 page table entries maps a I/O guest virtual address of the I/O virtual address space to a corresponding Level 2 guest physical address; and

cause a device driver of the Level 2 virtual machine to use the Level 2 page table for second level address translation.

18. The non-transitory machine-readable storage medium of claim 17 , wherein the Level 1 page table comprises a plurality of page table records, wherein each Level 1 page table record of the plurality of Level 1 page table records maps a Level 2 guest physical address of a Level 2 address space associated with the Level 2 virtual machine to a corresponding Level 0 host physical address of a Level 0 address space associated with the Level 0 hypervisor.

19. The non-transitory machine-readable storage medium of claim 17 , further comprising the processing device configured to:

grant, to the Level 2 virtual machine, direct access to the Level 2 page table.

20. The non-transitory machine-readable storage medium of claim 17 , further comprising the processing device configured to:

responsive to removing access, of the PCI device, to a memory page, update, by the Level 2 virtual machine, a page table entry of the Level 2 page table.