Gate driving circuit and driving method thereof and display panel

1. A gate driving circuit comprising 2×N stages of shift registers, the 2×N stages of shift registers comprising N first shift registers arranged alternately with N second shift registers,

wherein the N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals; and

wherein the N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals,

wherein K and N are both integers greater than 1, and K≤N;

wherein an input signal terminal if an n-th stage if first shift register in the N stages of first shift registers is coupled to an output signal terminal of an (n−i)-th stage of first shift register in the N stages of first shift registers, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register in the N stages of first shift registers, and

wherein an input signal terminal of an n-th stage of second shift register in the N stages of second shift registers is coupled to an output signal terminal of an (n−i)th stage of second shift register in the N stages of second shift registers, and a reset signal terminal of the n-th stage of second shift register is coupled to an output signal terminal of an (n+j)-th stage of second shift register in the N stages if second shift registers,

wherein n, i, and j are all integers greater than 0, K is an even number, 1<n<N, 1≤i≤K/2, and K/2+1≤j≤K−1.

2. The gate driving circuit of claim 1 , wherein K=6, i=3, and j=4.

3. The gate driving circuit of claim 1 , wherein K=4, i=2, and j=3.

4. The gate driving circuit of claim 1 , wherein K=8, i=4, and j=5.

5. The gate driving circuit of claim 1 ,

wherein input signal terminals of first to i-th stages of first shift registers in the N stages of first shift registers are configured to receive a first turn-on signal; and

wherein input signal terminals of first to i-th stages of second shift registers in the N stages of second shift registers are configured to receive a second turn-on signal.

6. The gate driving circuit of claim 1 , wherein reset signal terminals of (N−j+1)-th to N-th stages of first shift registers in the N stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers in the N stages of second shift registers are configured to receive a total reset signal.

7. The gate driving circuit of claim 1 , wherein the first shift registers are odd-numbered stages of shift registers in the 2×N stages of shift registers, and the second shift registers are even-numbered stages of shift registers in the 2×N stages of shift registers.

8. The gate driving circuit of claim 2 , wherein the first shift registers are odd-numbered stages of shift registers in the 2×N stages of shift registers, and the second shift registers are even-numbered stages of shift registers in the 2×N stages of shift registers.

9. The gate driving circuit of claim 1 ,

wherein the N first shift registers are divided into at least one group of K cascaded first shift registers, and clock signal terminals of the K cascaded first shift registers are configured to receive the K first clock signals respectively; and

wherein the N second shift registers are divided into at least one group of K cascaded second shift registers, and clock signal terminals of the K cascaded second shift registers are configured to receive the K second clock signals respectively.

10. The gate driving circuit of claim 1 ,

wherein each of the first shift registers is configured to output a first output signal at an output signal terminal of said each of the first shift registers based on a signal of an input signal terminal of said each of the first shift registers under control of a first clock signal received by a clock signal terminal of said each of the first shift registers, and reset a pull-up node of said each of the first shift registers under control of a signal of a reset signal terminal of said each of the first shift registers; and

wherein each of the second shift registers is configured to output a second output signal at an output signal terminal of said each of the second shift registers based on a signal of an input signal terminal of said each of the second shift registers under control of a second clock signal received by a clock signal terminal of said each of the second shift registers, and reset a pull-up node of said each of the second shift registers under control of a signal of a reset signal terminal of said each of the first shift registers.

11. The gate driving circuit of claim 1 ,

wherein each of the first shift registers is further configured to reset a pull-up node of said each of the first shift registers under control of a signal of a total reset terminal of said each of the first shift registers; and

wherein each of the second shift registers is further configured to reset a pull-up node of said each of the second shift registers under control of a signal of a total reset terminal of said each of the second shift registers,

wherein total reset terminals of the N first shift registers and total reset terminals of the N second shift registers are configured to receive a total reset signal.

12. A display panel comprising a gate driving circuit, wherein the gate driving circuit comprising 2×N stages of shift registers, the 2×N stages of shift registers comprising N first shift registers arranged alternately with N second shift registers,

wherein the N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals; and

wherein the N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals,

wherein K and N are both integers greater than 1, and K<N;

wherein an input signal terminal of an n-th stage of first shift register in the N stages of first shift registers is coupled to an output signal terminal of an (n−i)-th stage of first shift register in the N stages of first shift registers, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register in the N stages of first shift registers; and

wherein an input signal terminal of an n-th stage of second shift register in the N stages of second shift registers is coupled to an output signal terminal of an (n−i)-th stage of second shift register in the N stages of second shift registers, and a reset signal terminal of the n-th stage of second shift register is coupled to an output signal terminal of an (n+j)-th stage of second shift register in the N stages of second shift registers,

wherein n, i, and j are all integers greater than 0, K is an even number, 1<n<N, 1≤i≤K/2, and K/2+1≤j≤K−1.

13. A method of driving a gate driving circuit, wherein the gate driving circuit comprising 2×N stages of shift registers, the 2×N stages of shift registers comprising N first shift registers arranged alternately with N second shift registers, wherein the N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals; and wherein the N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals, wherein K and N are both integers greater than 1, and K<N; wherein an input signal terminal of an n-th stage of first shift register in the N stages of first shift registers is coupled to an output signal terminal of an (n−i)-th stage of first shift register in the N stages of first shift registers, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n−j)-th stage of first shift register in the N stages of first shift registers: and

wherein an input signal terminal of an n-th stage of second shift register in the N stages of second shift registers is coupled to an output signal terminal of an (n−i)-th stage of second shift register in the N stages of second shift registers, and a reset signal terminal of the n-th stage of second shift register is coupled to an output signal terminal of an (n−j)-th stage of second shift register in the N stages of second shift registers,

wherein n, i, and j are all integers greater than 0, K is an even numbers, 1<n<N, 1≤i≤K/2 and K/2+1≤j≤K−1,

the method comprising:

in a first mode, turning on the 2×N stages of shift registers, so that the N first shift registers of the 2×N stages of shift registers generate the N first output signals under control of the K first clock signals and the N second shift registers of the 2×N stages of shift registers generate the N second output signals under control of the K second clock signals; and

in a second mode, turning on the N first shift registers so that the N first shift registers generate the N first output signals under control of the K first clock signals, wherein the N first output signals are shifted sequentially, or turning on the N second shift registers in the second mode so that the N second shift registers generate the N second output signals under control of the K second clock signals, wherein the N second output signals are shifted sequentially.

14. The method of claim 13 , wherein, in the second mode,

the turning on the N first shift registers comprises: applying a valid first turn-on signal to the first to i-th stages of first shift registers in the N first shift registers, and applying an invalid second turn-on signal to the first to i-th stages of second shift registers in the N second shift registers; and

the turning on the N second shift registers comprises: applying a valid second turn-on signal to the first to i-th stages of second shift registers in the N second shift registers, and applying an invalid first turn-on signal to the first to i-th stages of first shift registers in the N first shift registers,

wherein i is an integer and 1≤i≤K/2.