Sample-and-hold amplifier and semiconductor device including the same
A sample-and-hold amplification circuit can include a sampling circuit configured to sample first and second input signals in response to first and second control signals to generate first and second sampled signals, an amplification circuit configured to amplify a voltage difference between the first and second sampled signals to generate first and second output signals, and an offset compensation circuit configured to form a first path between input and output terminals of the amplification circuit in response to the first control signal to store an offset of the input terminal and form a second path between the input and output terminals in response to the second control signal to reflect the offset to the output terminal.
1. A sample-and-hold amplification circuit, comprising:
a sampling circuit configured to sample first and second input signals in response to first and second control signals to generate first and second sampled signals;
an amplification circuit configured to amplify a voltage difference between the first and second sampled signals to generate first and second output signals; and
an offset compensation circuit configured to form a first path between input and output terminals of the amplification circuit in response to the first control signal to store an offset of the input terminal and form a second path between the input and output terminals in response to the second control signal to reflect the offset to the output terminal,
wherein the offset compensation circuit comprises a compensation capacitor which is coupled between the input and output terminals of the amplification circuit via the first path when the first control signal is activated or the second path when the second control signal is activated.
2. The sample-and-hold amplification circuit according to claim 1 , wherein the offset compensation circuit comprises:
an offset storage circuit configured to form the first path between a first input terminal and a second output terminal of the amplification circuit and between a second input terminal and a first output terminal of the amplification circuit, in response to the first control signal; and
an offset reflection circuit configured to form the second path between the first input terminal and the first output terminal of the amplification circuit and between the second input terminal and the second terminal of the amplification circuit, in response to the second control signal.
3. The sample-and-hold amplification circuit according to claim 2 , wherein the offset storage circuit comprises:
first and second capacitors individually coupled to the first and second output terminals of the amplification circuit;
a first switch coupled between the first capacitor and the second output terminal of the amplification circuit and configured to be turned on in response to the first control signal; and
a second switch coupled between the second capacitor and the first output terminal of the amplification circuit and configured to be turned on in response to the first control signal.
4. The sample-and-hold amplification circuit according to claim 3 , wherein the offset reflection circuit comprises:
the first and second capacitors;
a third switch coupled between the first capacitor and the first output terminal of the amplification circuit and configured to be turned on in response to the second control signal; and
a fourth switch coupled between the second capacitor and the second output terminal of the amplification circuit and configured to be turned on in response to the second control signal.
5. The sample-and-hold amplification circuit according to claim 1 , wherein the sampling circuit comprises:
a first sampling switch turned on in response to the first control signal to transfer the first and second input signals;
a second sampling switch turned on in response to the second control signal to transfer the first and second input signals; and
a sampling capacitor between the first and second sampling switches and the amplification circuit.
6. The sample-and-hold amplification circuit according to claim 5 , wherein the first sampling circuit comprises:
a first switch turned on in response to the first control signal to transfer the first input signal to a first capacitor of the sampling capacitor; and
a second switch turned on in response to the first control signal to transfer the second input signal to a second capacitor of the sampling capacitor.
7. The sample-and-hold amplification circuit according to claim 6 , wherein the second sampling circuit comprises:
a third switch turned on in response to the second control signal to transfer the first input signal to the second capacitor of the sampling capacitor; and
a fourth switch turned on in response to the second control signal to transfer the second input signal to the first capacitor of the sampling capacitor.
8. The sample-and-hold amplification circuit according to claim 1 , wherein the first and second control signals comprise two clock signals having phases which are complementary to each other and are not overlapped with each other.
9. The sample-and-hold amplification circuit according to claim 1 , wherein the amplification circuit comprises:
an operational amplifier coupled between the input terminal and the output terminal to generate the first and second output signals;
a reset switch turned on in response to the first control signal to form a feedback loop between the input terminal and the output terminal; and
a feedback capacitor coupled in parallel with the reset switch between the input terminal and the output terminal.
10. The sample-and-hold amplification circuit according to claim 9 , wherein the compensation capacitor is coupled in parallel with the feedback capacitor when the second control signal is activated.
11. The sample-and-hold amplification circuit according to claim 9 , wherein the compensation capacitor and the feedback capacitor have the same capacitance.
12. A semiconductor device, comprising:
a temperature sensing circuit configured to generate first and second input signals, wherein a voltage difference between the first and second input signals increases in a proportion to temperature;
an amplification circuit configured to amplify the voltage difference between the first and second input signals to generate first and second output signals; and
an analog-to-digital conversion circuit configured to convert a voltage difference between the first and second output signals into a digital signal including information of the temperature,
wherein the amplification circuit is further configured to form a first path between input and output terminals of the amplification circuit in response to the first control signal to store an offset of the input terminal and form a second path between the input and output terminals in response to the second control signal to reflect the offset to the output terminal, and
wherein the amplification circuit comprises a compensation capacitor which is coupled between the input and output terminals of the amplification circuit via the first path when the first control signal is activated or the second path when the second control signal is activated.
13. The semiconductor device according to claim 12 , wherein the amplification circuit comprises:
an offset storage circuit configured to form the first path between a first input terminal and a second output terminal of the amplification circuit and between a second input terminal and a first output terminal of the amplification circuit, in response to the first control signal; and
an offset reflection circuit configured to form the second path between the first input terminal and the first output terminal of the amplification circuit and between the second input terminal and the second output terminal of the amplification circuit, in response to the second control signal.
14. The semiconductor device according to claim 12 , wherein the amplification circuit comprises:
an operational amplifier coupled between the input terminal and the output terminal to generate the first and second output signals;
a reset switch turned on in response to the first control signal to form a feedback loop between the input terminal and the output terminal; and
a feedback capacitor coupled in parallel with the reset switch between the input terminal and the output terminal.
15. The semiconductor device according to claim 14 , wherein the compensation capacitor and the feedback capacitor have the same capacitance.
16. The semiconductor device according to claim 12 , wherein the first and second control signals comprise two clock signals having phases which are complementary to each other and are not overlapped with each other.