Post package repair failure memory location reporting system
A PPR memory location reporting system includes BIOS coupled to a non-volatile memory system and a volatile memory system. During boot operations, the BIOS identifies a memory location identifier in the non-volatile memory system for a memory location that is included in the volatile memory system and that is associated with PPR, performs PPR operations on the memory location, and determines that the PPR operations on the memory location have failed. In response to determining that the PPR operations on the memory location have failed, the BIOS stores the memory location identifier in a boot error report table that is configured for use by an operating system to prevent use of the memory location by the operating system, and reserves the memory location identifier in a memory map that is configured for use by the operating system to prevent use of the memory location by the operating system.
1. A Post Package Repair (PPR) memory location reporting system, comprising:
a non-volatile memory system including at least one non-volatile memory device;
a volatile memory system including at least one volatile memory device;
a Basic Input/Output System (BIOS) that is coupled to the non-volatile memory system and the volatile memory system, wherein the BIOS is configured, during boot operations, to:
identify, in the non-volatile memory system, a memory location identifier for a memory location that is included in the volatile memory system and that is associated with Post Package Repair (PPR);
perform, in response to identifying that the memory location identifier is associated with PPR, PPR operations on the memory location;
determine that the PPR operations on the memory location have failed; and
provide, in at least one operating-system-accessible memory-location-use-prevention data structure in response to determining that the PPR operations on the memory location have failed, the memory location identifier; and
an operating system that is coupled to the volatile memory system, wherein the operating system is configured, during runtime operations, to:
use the at least one operating-system-accessible memory-location-use-prevention data structure, wherein the at least one operating-system-accessible memory-location-use-prevention data structure prevents the operating system from using the memory location upon which the PPR operations failed in the volatile memory system that has exhausted its PPR resources.
2. The system of claim 1 , further comprising:
a processing system that is coupled to the volatile memory system and the BIOS, wherein the BIOS is configured, during runtime operations, to
receive, from the processing system, the memory location identifier; and
associate the memory location identifier with the PPR in the non-volatile memory system.
3. The system of claim 1 , wherein the BIOS is configured, during runtime operations, to:
associate, in the non-volatile memory system in response to determining that the PPR operations on the memory location have failed, the memory location identifier with failed PPR operations.
4. The system of claim 1 , wherein the BIOS is configured, during boot operations, to:
associate, in the non-volatile memory system in response to determining that the PPR operations on the memory location have failed, the memory location identifier that is associated with the failed PPR operations with a memory module identifier for a memory module that is connected to a first memory module connector and that includes a memory device having the memory location.
5. The system of claim 1 , wherein the at least one operating-system-accessible memory-location-use-prevention data structure includes at least one of a boot error report table and a memory map.
6. The system of claim 5 , wherein the boot error report table is an Advanced Configuration and Power Interface (ACPI) Boot Error Report Table (BERT), and wherein the memory map is a Universally Extensible Firmware Interface (UEFI) memory map.
7. An Information Handling System (IHS), comprising:
a Basic Input/Output System (BIOS) processing system;
a BIOS memory system that includes at least one BIOS memory device, that is coupled to the BIOS processing system, and that includes instructions that, when executed by the BIOS processing system, cause the BIOS processing system to provide a BIOS engine that is configured, during boot operations, to:
identify, in a non-volatile memory system, a memory location identifier for a memory location that is included in a volatile memory system and that is associated with Post Package Repair (PPR);
perform, in response to identifying that the memory location identifier is associated with PPR, PPR operations on the memory location;
determine that the PPR operations on the memory location have failed; and
provide, in at least one operating-system-accessible memory-location-use-prevention data structure in response to determining that the PPR operations on the memory location have failed, the memory location identifier;
an operating system processing system; and
an operating system memory system that includes at least one operating system memory device, that is coupled to the operating system processing system, and that includes instructions that, when executed by the operating system processing system, cause the operating system processing system to provide an operating system that is configured, during runtime operations, to:
use the at least one operating-system-accessible memory-location-use-prevention data structure, wherein the at least one operating-system-accessible memory-location-use-prevention data structure prevents the operating system from using the memory location upon which the PPR operations failed in the volatile memory system that has exhausted its PPR resources.
8. The IHS of claim 7 , wherein the BIOS engine is configured, during runtime operations, to:
receive, from a primary processing system, the memory location identifier; and
associate the memory location identifier with the PPR in the non-volatile memory system.
9. The IHS of claim 7 , wherein the BIOS engine is configured, during runtime operations, to:
associate, in the non-volatile memory system in response to determining that the PPR operations on the memory location have failed, the memory location identifier with failed PPR operations.
10. The IHS of claim 7 , wherein the BIOS engine is configured, during boot operations, to:
associate, in the non-volatile memory system in response to determining that the PPR operations on the memory location have failed, the memory location identifier that is associated with the failed PPR operations with a memory module identifier for a memory module that is connected to a first memory module connector and that includes a memory device having the memory location.
11. The IHS of claim 7 , wherein the at least one operating-system-accessible memory-location-use-prevention data structure includes at least one of a boot error report table and a memory map.
12. The IHS of claim 11 , wherein the boot error report table is an Advanced Configuration and Power Interface (ACPI) Boot Error Report Table (BERT).
13. The IHS of claim 11 , wherein the memory map is a Universally Extensible Firmware Interface (UEFI) memory map.
14. A method for reporting Post Package Repair (PPR) failure memory locations, comprising:
identifying, by a Basic Input/Output System (BIOS) in a non-volatile memory system, a memory location identifier for a memory location that is included in a volatile memory system and that is associated with Post Package Repair (PPR);
performing, by the BIOS in response to identifying that the memory location identifier is associated with PPR, PPR operations on the memory location;
determining, by the BIOS, that the PPR operations on the memory location have failed;
providing, by the BIOS in at least one operating-system-accessible memory-location-use-prevention data structure in response to determining that the PPR operations on the memory location have failed, the memory location identifier;
using, by an operating system, the at least one operating-system-accessible memory-location-use-prevention data structure, wherein the at least one operating-system-accessible memory-location-use-prevention data structure prevents the operating system from using the memory location upon which the PPR operations failed in the volatile memory system that has exhausted its PPR resources.
15. The method of claim 14 , further comprising:
receiving, by the BIOS from a primary processing system, the memory location identifier; and
associating, by the BIOS, the memory location identifier with the PPR in the non-volatile memory system.
16. The method of claim 14 , further comprising:
associating, by the BIOS in the non-volatile memory system in response to determining that the PPR operations on the memory location have failed, the memory location identifier with failed PPR operations.
17. The method of claim 14 , further comprising:
associating, by the BIOS in the non-volatile memory system in response to determining that the PPR operations on the memory location have failed, the memory location identifier that is associated with the failed PPR operations with a memory module identifier for a memory module that is connected to a first memory module connector and that includes a memory device having the memory location.
18. The method of claim 14 , wherein the at least one operating-system-accessible memory-location-use-prevention data structure includes at least one of a boot error report table and a memory map.
19. The method of claim 18 , wherein the boot error report table is an Advanced Configuration and Power Interface (ACPI) Boot Error Report Table (BERT).
20. The method of claim 18 , wherein the memory map is a Universally Extensible Firmware Interface (UEFI) memory map.