Compression and interleaving of spatially proximate data
Methods, systems and apparatuses may provide for technology that identifies first graphics data that is associated with spatially proximate positions. The technology identifies second graphics data that is associated with spatially proximate positions, and interleaves the first and the second graphics data across a plurality of storage tiles.
1. A computing system comprising:
a display to present an image; and
a graphics processor coupled to the display, wherein the graphics processor includes logic coupled to one or more substrates, the logic to:
identify first graphics data that is to be associated with spatially proximate positions;
identify second graphics data that is to be associated with spatially proximate positions; and
interleave the first and the second graphics data across a plurality of storage tiles by a storage of a first part of the first graphics data and a second part of the second graphics data into a first memory bank, and a storage of a third part of the first graphics data and a fourth part of the second graphics data into a second memory bank, wherein the first, second, third and fourth parts include textures or the first, second, third and fourth parts include anti-aliasing samples.
2. The computing system of claim 1 , wherein:
the anti-aliasing samples include first and second anti-aliasing samples;
the first graphics data includes the first anti-aliasing samples, wherein the first anti-aliasing samples are associated with a first pixel block, wherein pixels of the first pixel block are to share a shading result based on the first anti-aliasing samples; and
the second graphics data includes the second anti-aliasing samples, wherein the second anti-aliasing samples are associated with a second pixel block, wherein pixels of the second pixel block are to share a shading result based on the second anti-aliasing samples.
3. The computing system of claim 2 , wherein the logic coupled to the one or more substrates is to:
store a first sample of the first anti-aliasing samples and a first sample of the second anti-aliasing samples in a first storage tile of the plurality of storage tiles, wherein the first storage tile is the first memory bank.
4. The computing system of claim 3 , wherein the logic coupled to the one or more substrates is to:
store a second sample of the first anti-aliasing samples and a second sample of the second anti-aliasing samples in a second storage tile of the plurality of storage tiles, wherein the second storage tile is the second memory bank.
5. The computing system of claim 1 , wherein:
the textures include a first plurality of textures associated with a first Z slice and a second plurality of textures associated with a second Z slice;
the first graphics data is associated with the first plurality of textures; and
the second graphics data is associated with the second plurality of textures.
6. The computing system of claim 5 , wherein the logic coupled to the one or more substrates is to:
store a first texture of the first plurality of textures and a first texture of the second plurality of textures in a first storage tile of the plurality of storage tiles, wherein the first storage tile is the first memory bank.
7. The computing system of claim 6 , wherein the logic coupled to the one or more substrates is to:
store a second texture of the first plurality of textures and a second texture of the second plurality of textures in a second storage tile of the plurality of storage tiles, wherein the second storage tile is the second memory bank.
8. The computing system of claim 1 , wherein the plurality of storage tiles is to include a plurality of pages of a dynamic random-access memory.
9. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
identify first graphics data that is to be associated with spatially proximate positions;
identify second graphics data that is to be associated with spatially proximate positions; and
interleave the first and the second graphics data across a plurality of storage tiles by a storage of a first part of the first graphics data and a second part of the second graphics data into a first memory bank, and a storage of a third part of the first graphics data and a fourth part of the second graphics data into a second memory bank, wherein the first, second, third and fourth parts include textures or the first, second, third and fourth parts include anti-aliasing samples.
10. The semiconductor apparatus of claim 9 , wherein:
the anti-aliasing samples include first and second anti-aliasing samples;
the first graphics data includes the first anti-aliasing samples, wherein the first anti-aliasing samples are associated with a first pixel block, wherein pixels of the first pixel block are to share a shading result based on the first anti-aliasing samples; and
the second graphics data includes the second anti-aliasing samples, wherein the second anti-aliasing samples are associated with a second pixel block, wherein pixels of the second pixel block are to share a shading result based on the second anti-aliasing samples.
11. The semiconductor apparatus of claim 10 , wherein the logic coupled to the one or more substrates is to:
store a first sample of the first anti-aliasing samples and a first sample of the second anti-aliasing samples in a first storage tile of the plurality of storage tiles, wherein the first storage tile is the first memory bank.
12. The semiconductor apparatus of claim 11 , wherein the logic coupled to the one or more substrates is to:
store a second sample of the first anti-aliasing samples and a second sample of the second anti-aliasing samples in a second storage tile of the plurality of storage tiles, wherein the second storage tile is the second memory bank.
13. The semiconductor apparatus of claim 9 , wherein:
the textures include a first plurality of textures associated with a first Z slice and a second plurality of textures associated with a second Z slice;
the first graphics data is associated with the first plurality of textures; and
the second graphics data is associated with the second plurality of textures.
14. The semiconductor apparatus of claim 13 , wherein the logic coupled to the one or more substrates is to:
store a first texture of the first plurality of textures and a first texture of the second plurality of textures in a first storage tile of the plurality of storage tiles, wherein the first storage tile is the first memory bank.
15. The semiconductor apparatus of claim 14 , wherein the logic coupled to the one or more substrates is to:
store a second texture of the first plurality of textures and a second texture of the second plurality of textures in a second storage tile of the plurality of storage tiles, wherein the second storage tile is the second memory bank.
16. The semiconductor apparatus of claim 9 , wherein the plurality of storage tiles is to includes a plurality of pages of a dynamic random-access memory.
17. The semiconductor apparatus of claim 9 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.
18. A method comprising:
identifying first graphics data that is associated with spatially proximate positions;
identifying second graphics data that is associated with spatially proximate positions; and
interleaving the first and the second graphics data across a plurality of storage tiles by storing a first part of the first graphics data and a second part of the second graphics data into a first memory bank, and storing a third part of the first graphics data and a fourth part of the second graphics data into a second memory bank, wherein the first, second, third and fourth parts include textures or the first, second, third and fourth parts include anti-aliasing samples.
19. The method of claim 18 , wherein:
the anti-aliasing samples include first and second anti-aliasing samples;
the first graphics data includes the first anti-aliasing samples, wherein the first anti-aliasing samples are associated with a first pixel block, wherein pixels of the first pixel block share a shading result based on the first anti-aliasing samples; and
the second graphics data includes the second anti-aliasing samples, wherein the second anti-aliasing samples are associated with a second pixel block, wherein pixels of the second pixel block share a shading result based on the second anti-aliasing samples.
20. The method of claim 19 , further comprising:
storing a first sample of the first anti-aliasing samples and a first sample of the second anti-aliasing samples in a first storage tile of the plurality of storage tiles, wherein the first storage tile is the first memory bank.
21. The method of claim 20 , further comprising:
storing a second sample of the first anti-aliasing samples and a second sample of the second anti-aliasing samples in a second storage tile of the plurality of storage tiles, wherein the second storage tile is the second memory bank.
22. The method of claim 18 , wherein:
the textures include a first plurality of textures associated with a first Z slice and a second plurality of textures associated with a second Z slice;
the first graphics data is associated with the first plurality of textures; and
the second graphics data is associated with the second plurality of textures.
23. The method of claim 22 , further comprising:
storing a first texture of the first plurality of textures and a first texture of the second plurality of textures in a first storage tile of the plurality of storage tiles, wherein the first storage tile is the first memory bank.
24. The method of claim 23 , further comprising:
storing a second texture of the first plurality of textures and a second texture of the second plurality of textures in a second storage tile of the plurality of storage tiles, wherein the second storage tile is the second memory bank.
25. The method of claim 18 , wherein the plurality of storage tiles includes a plurality of pages of a dynamic random-access memory.