IP Library Granted Patent US 11,916,475
Granted Patent B2
US 11,916,475 · App. 17/357,884 · Granted Feb 27, 2024

Power semiconductor package

Inventor: David Giuliano (San Diego, CA)
Assignee: PSEMI CORPORATION
H02M3/003H02M1/0006H02M1/0095H02M3/158
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Quick Facts
Patent No.
US 11,916,475
App. No.
17/357,884
Granted
Feb 27, 2024
Kind
B2
Abstract

Subject matter disclosed herein may relate to semiconductor devices, and may more particularly relate to power semiconductor packages, for example.

Claims (57)

1. An apparatus, comprising:

a multi-level power converter including a plurality of power semiconductor packages, wherein the plurality of power semiconductor packages individually comprise:

a power transfer path comprising at least a high-side switch and a low-side switch each comprising a vertical field effect transistor including a first node and a second node arranged vertically with respect to each other along a direction perpendicular to a major surface of an individual power semiconductor package;

a first terminal coupled to the first node of the high-side switch;

a second terminal coupled to the second node of the low-side switch;

a high-side switch terminal coupled to the second node of the high-side switch; and

a low-side switch terminal coupled to the first node of the low-side switch,

wherein the high-side switch terminal and the low-side switch terminal comprise separate terminals, and

at least one of the first terminal or the second terminal includes terminal lead frame contacts arranged along an edge of the individual power semiconductor package.

2. The apparatus of claim 1 , wherein the plurality of power semiconductor packages individually further comprise:

a high-side driver coupled to a control terminal of the high-side switch; and

a low-side driver coupled to a control terminal of the low-side switch.

3. The apparatus of claim 2 , wherein the plurality of power semiconductor packages individually further comprise:

a first boot supply terminal coupled to the high-side driver; and

a second boot supply terminal coupled to the low-side driver, wherein the first boot supply terminal is separate from the second boot supply terminal.

4. The apparatus of claim 3 , wherein the multi-level power converter further comprises:

at least one first boot capacitor coupled between the high-side switch terminal and the first boot supply terminal for a respective at least a first one of the plurality of power semiconductor packages; and

at least one second boot capacitor coupled between the second terminal coupled to the second node of the low-side switch and a second boot supply terminal for the respective at least the first one of the plurality of power semiconductor packages.

5. The apparatus of claim 1 , wherein at least one of the plurality of power semiconductor packages to include a controller to affect operation of the respective high-side switches and low-side switches of the plurality of power semiconductor packages.

6. The apparatus of claim 5 , wherein a controller of a first of the plurality of power semiconductor packages to provide at least one control signal to at least one other of the plurality of power semiconductor packages.

7. The apparatus of claim 1 , wherein multi-level power converter comprises a multi-level-buck arrangement.

8. The apparatus of claim 7 , wherein the first terminal coupled to the first node of the high-side switch for a first of the plurality of power semiconductor packages comprises a higher voltage node for the multi-level buck arrangement.

9. The apparatus of claim 8 , wherein for one or more of the plurality of power semiconductor packages the high-side switch terminal and the low-side switch terminal are electrically connected to a lower voltage node for the multi-level buck arrangement.

10. The apparatus of claim 1 , wherein the high-side switch and the low-side switch are arranged in a horizontal fashion.

11. The apparatus of claim 1 , wherein the vertical field effect transistor is a vertical metal oxide semiconductor field effect transistor.

12. The apparatus of claim 1 , wherein the plurality of power semiconductor packages individually comprise an integrated circuit comprising driver circuitry, and

the driver circuitry is electrically coupled to gate regions of the high-side switch and the low-side switch via one or more bond wires.

13. An apparatus, comprising:

a multi-level power converter including a plurality of power semiconductor packages, wherein the plurality of power semiconductor packages individually comprise:

a power transfer path comprising at least a high-side switch and a low-side switch each comprising a vertical field effect transistor including a first node and a second node arranged vertically with respect to each other along a direction perpendicular to a major surface of an individual power semiconductor package;

a first terminal coupled to the first node of the high-side switch;

a second terminal coupled to the second node of the low-side switch;

a high-side switch terminal coupled to the second node of the high-side switch; and

a low-side switch terminal coupled to the first node of the low-side switch,

wherein the high-side switch terminal and the low-side switch terminal comprise separate terminals,

the plurality of power semiconductor packages individually comprise an integrated circuit comprising driver circuitry,

the plurality of power semiconductor packages individually comprise lead frame contacts for receiving control signals,

the driver circuitry is electrically coupled to the lead frame contacts via one or more bond wires, and

the lead frame contacts for receiving control signals are arranged along an edge of the individual power semiconductor package.

14. An apparatus, comprising:

a multi-level power converter including a plurality of power semiconductor packages, wherein the plurality of power semiconductor packages individually comprise:

a power transfer path comprising at least a high-side switch and a low-side switch each comprising a vertical field effect transistor including a first node and a second node arranged vertically with respect to each other along a direction perpendicular to a major surface of an individual power semiconductor package;

a first terminal coupled to the first node of the high-side switch;

a second terminal coupled to the second node of the low-side switch;

a high-side switch terminal coupled to the second node of the high-side switch; and

a low-side switch terminal coupled to the first node of the low-side switch,

wherein the high-side switch terminal and the low-side switch terminal comprise separate terminals,

the high-side switch terminal is coupled to the second node of the high-side switch via a first copper clip, and

the low-side switch terminal is coupled to the first node of the low-side switch via a second copper clip.

15. The apparatus of claim 14 , wherein the first copper clip vertically overlaps at least portion of the high-side switch.

16. The apparatus of claim 14 , wherein the second copper clip vertically overlaps at least portion of the low-side switch.

17. The apparatus of claim 14 , wherein the plurality of power semiconductor packages individually further comprise:

a high-side driver coupled to a control terminal of the high-side switch; and

a low-side driver coupled to a control terminal of the low-side switch.

18. The apparatus of claim 14 , wherein at least one of the plurality of power semiconductor packages to include a controller to affect operation of the respective high-side switches and low-side switches of the plurality of power semiconductor packages.

19. The apparatus of claim 14 , wherein the high-side switch and the low-side switch are arranged in a horizontal fashion.

20. The apparatus of claim 14 , wherein at least one of the first terminal or the second terminal includes terminal lead frame contacts arranged along an edge of the individual power semiconductor package.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2024
From: PSEMI CORPORATION
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 066875/0457 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNMENT PREVIOUSLY RECORDED AT REEL: 059533 FRAME: 0907. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Nov 3, 2023
From: GIULIANO, DAVID
To: PSEMI CORPORATION
Reel/Frame 065459/0937 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2022
From: GIULIANO, DAVID
To: PSEMI CORPORATION
Reel/Frame 059533/0907 →
Continuity (1)
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