Computing chassis including removeable midplanes
A computing chassis, including: a first storage processor assembly; a second storage processor assembly; a first midplane, wherein the first storage processor assembly and the second storage processor assembly are coupled concurrently to the first midplane; and a second midplane, wherein the first storage processor assembly and the second storage processor assembly are coupled concurrently to the second midplane, wherein communication between the first storage processor assembly and the second storage processor assembly is through the first midplane and the second midplane independently.
1. A computing chassis, including:
a first storage processor assembly;
a second storage processor assembly;
a first midplane positioned along a first edge of the computing chassis, wherein the first storage processor assembly and the second storage processor assembly are coupled concurrently to the first midplane;
a second midplane, wherein the first storage processor assembly and the second storage processor assembly are coupled concurrently to the second midplane; and
a third midplane positioned along the first edge of the computing chassis, wherein the first storage processor assembly and the second processor assembly are coupled concurrently to the third midplane,
wherein communication between the first storage processor assembly and the second storage processor assembly is through the first midplane, the second midplane, and the third midplane independently.
2. The computing chassis of claim 1 , wherein the second midplane is positioned along a second edge of the computing chassis, wherein the second edge is opposite to the first edge.
3. The computing chassis of claim 2 , wherein at least a portion of the first storage processor assembly and the second storage processor assembly are physically defined between the first and the second midplanes.
4. The computing chassis of claim 1 , further comprising:
a third storage processor assembly,
wherein the first storage processor assembly, the second storage processor assembly, and the third storage processor assembly are coupled concurrently to the first midplane,
wherein the first storage processor assembly, the second storage processor assembly, and the third storage processor assembly are coupled concurrently to the second midplane.
5. The computing chassis of claim 1 , wherein the first and the second midplanes are removable from the computing chassis.
6. The computing chassis of claim 1 , wherein the second midplane is redundant to the first midplane.
7. The computing chassis of claim 1 , further comprising one or more storage devices coupled to one or more of the first storage processor assembly and the second storage processor assembly.
8. An information handling system, comprising:
a processor;
memory media storing instructions executable by the processor to perform operations;
a computing chassis, including:
a first storage processor assembly;
a second storage processor assembly;
a first midplane positioned along a first edge of the computing chassis, wherein the first storage processor assembly and the second storage processor assembly are coupled concurrently to the first midplane;
a second midplane, wherein the first storage processor assembly and the second storage processor assembly are coupled concurrently to the second midplane; and
a third midplane positioned along the first edge of the computing chassis, wherein the first storage processor assembly and the second processor assembly are coupled concurrently to the third midplane,
wherein communication between the first storage processor assembly and the second storage processor assembly is through the first midplane, the second midplane, and the third midplane independently.
9. The information handling system of claim 8 , wherein the second midplane is positioned along a second edge of the computing chassis, wherein the second edge is opposite to the first edge.
10. The information handling system of claim 9 , wherein at least a portion of the first storage processor assembly and the second storage processor assembly are physically defined between the first and the second midplanes.
11. The information handling system of claim 8 , the computing chassis further comprising:
a third storage processor assembly,
wherein the first storage processor assembly, the second storage processor assembly, and the third storage processor assembly are coupled concurrently to the first midplane,
wherein the first storage processor assembly, the second storage processor assembly, and the third storage processor assembly are coupled concurrently to the second midplane.
12. The information handling system of claim 8 , wherein the first and the second midplanes are removable from the computing chassis.
13. The information handling system of claim 8 , wherein the second midplane is redundant to the first midplane.
14. The information handling system of claim 8 , further comprising one or more storage devices coupled to one or more of the first storage processor assembly and the second storage processor assembly.