NAND flash memory with vertical cell stack structure and method for manufacturing same
Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
1. A method for manufacturing a NAND flash memory device with a vertical cell stack structure, the method comprising:
photolithographically defining, at a semiconductor surface, a first source line region, a second source line region, and a photo alignment mark, wherein the first source line region and the second source line region are separated from each other at the semiconductor surface;
then depositing alternating first and second cell stack layers over at least the first source line region and the second source line region;
etching a plurality of pillar holes through the alternating first and second cell stack layers at locations defined in alignment with the photo alignment mark;
filling each pillar hole with at least a semiconductor material and a dielectric filler; and
etching a plurality of slits through the alternating first and second cell stack layers.
2. The method of claim 1 , wherein the defining step comprises:
forming an n-type conductive layer at the semiconductor surface;
then, using a photolithographically patterned mask, etching at least one trench into the semiconductor surface, one of the at least one trench separating the first source line region and the second source line region from each other; and
filling the at least one trench with a dielectric material.
3. The method of claim 2 , wherein each of the plurality of pillar holes extends deeper from the semiconductor surface than a depth of the n-type conductive layer.
4. The method of claim 1 , wherein the defining step comprises:
depositing a hard mask layer over the semiconductor surface;
using a photolithographically patterned mask, etching portions of the hard mask layer to define locations of the first and second source lines and the photo alignment mark;
ion implanting locations of the semiconductor surface exposed by the etched hard mask layer with an n-type dopant;
applying a masking layer over the hard mask layer at the locations of first and second source line regions to expose the location of the photo alignment mark;
then etching into the semiconductor surface at the location of the photo alignment mark; and
removing the hard mask layer.
5. The method of claim 1 , wherein the location of at least one of the plurality of pillar holes is between the first and second source line regions.
6. The method of claim 1 , wherein the defining step comprises:
using a photolithographically patterned mask, etching at least one trench into the semiconductor surface;
filling the at least one trench with a dielectric material; and
then forming an n-type conductive layer at the semiconductor surface on opposite sides of at least one trench to define the first source line region and the second source line region.
7. The method of claim 6 , wherein each of the plurality of pillar holes extends deeper from the semiconductor surface than a depth of the n-type conductive layer.