Apparatus, memory controller, memory device, memory system, and method for clock switching and low power consumption
View Patent ↗In an apparatus, a memory controller, a memory device, and a method for switching frequencies of clock signals to reduce power consumption, when the memory device performs an internal operation according to a command of the memory controller, a frequency of a clock signal of the memory controller is changed. The memory controller switches the frequency of the clock signal to a low frequency according to assertion of a status signal that indicates a busy operation status of the memory device according to the command, and switches the frequency of the clock signal to a high frequency according to de-assertion of the status signal that indicates a ready operation status of the memory device.
1. An apparatus comprising:
a plurality of signal pins respectively connected to an external device through a plurality of signal lines; and
a clock control circuit configured to instruct the external device through some of the plurality of signal pins to perform one operation having a first operation mode and a second operation mode, and configured to generate a clock signal relating to the first operation mode and the second operation mode for the one operation of the external device,
wherein the clock control circuit is configured to switch a frequency of the clock signal to a first frequency during the first operation mode of the one operation, and switch the frequency of the clock signal to a second frequency different from the first frequency during the second operation mode according to de-assertion of a status signal of the external device provided to the apparatus from the external device, and
wherein the external device comprises a nonvolatile memory device, and
wherein the one operation is a read operation of the nonvolatile memory device, and
the clock control circuit is configured to generate the clock signal having a low frequency while the nonvolatile memory device reads data stored in a memory cell of the nonvolatile memory device, and generate the clock signal having a high frequency while the nonvolatile memory device transmits the data read from the nonvolatile memory device to the apparatus.
2. The apparatus of claim 1 , wherein the first operation mode is a low-power operation mode associated with the clock signal having the first frequency, and the second operation mode is a high-power operation mode associated with the clock signal having the second frequency.
3. The apparatus of claim 1 , wherein the first frequency is a low frequency, and the second frequency is a high frequency.
4. The apparatus of claim 1 , wherein the clock signal does not toggle while the nonvolatile memory device reads the data stored in the memory cell.
5. The apparatus of claim 1 , wherein the apparatus receives the status signal indicating a busy status during the first operation mode of the one operation performed by the external device through a signal pin from among the plurality of signal pins, and
the clock control circuit is configured to generate the clock signal having the first frequency which is set to a relatively low frequency based on the status signal indicating the busy status.
6. The apparatus of claim 5 , wherein the apparatus receives the status signal de-asserting to a ready status during the second operation mode in the one operation performed by the external device, and
the clock control circuit is configured to generate the clock signal having the second frequency which is set to a relatively high frequency based on the status signal in the ready status.
7. An apparatus comprising:
a plurality of signal pins respectively connected to an external device through a plurality of signal lines; and
a clock control circuit configured to instruct the external device through some of the plurality of signal pins to perform one operation having a first operation mode and a second operation mode, and configured to generate a clock signal relating to the first operation mode and the second operation mode for the one operation of the external device,
wherein the clock control circuit is configured to switch a frequency of the clock signal to a first frequency during the first operation mode of the one operation, and switch the frequency of the clock signal to a second frequency different from the first frequency during the second operation mode according to de-assertion of a status signal of the external device provided to the apparatus from the external device, and
wherein the external device comprises a nonvolatile memory device,
wherein the one operation is a write operation of the nonvolatile memory device, and
the clock control circuit is configured to generate the clock signal having a high frequency while transmitting write data to the nonvolatile memory device, and generate the clock signal having a low frequency while the nonvolatile memory device programs the write data to memory cells of the nonvolatile memory device.
8. The apparatus of claim 7 , wherein the clock signal does not toggle while the write data is programmed to the memory cells of the nonvolatile memory device.
9. An apparatus comprising:
a plurality of signal pins respectively connected to an external device through a plurality of signal lines; and
a clock control circuit configured to instruct the external device through some of the plurality of signal pins to perform one operation having a first operation mode and a second operation mode, and configured to generate a clock signal relating to the first operation mode and the second operation mode for the one operation of the external device,
wherein the clock control circuit is configured to switch a frequency of the clock signal to a first frequency during the first operation mode of the one operation, and switch the frequency of the clock signal to a second frequency different from the first frequency during the second operation mode according to de-assertion of a status signal of the external device provided to the apparatus from the external device, and
wherein the external device comprises a nonvolatile memory device,
wherein the clock control circuit is configured to set the second frequency of the clock signal to be relatively higher when the nonvolatile memory device performs a read operation of reading data stored in memory cells of the nonvolatile memory device than when the nonvolatile memory device performs a write operation of programming data to the memory cells.