IP Library Granted Patent US 11,631,468
Granted Patent B2
US 11,631,468 · App. 17/373,012 · Granted Apr 18, 2023

Non-volatile semiconductor storage device

Inventor: Naoki Matsunaga (Tokyo, JP)
Assignee: KIOXIA CORPORATION
G11C16/26G06F3/064G06F3/0619G06F3/0655G06F3/0679G06F11/1068G11C11/5628G11C11/5642G11C16/04G11C16/0483G11C16/06G11C16/3404G11C16/349G11C16/3495G11C29/52
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Quick Facts
Patent No.
US 11,631,468
App. No.
17/373,012
Granted
Apr 18, 2023
Kind
B2
Abstract

According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

Claims (48)

1. A memory system connectable to a host apparatus including a display device, the memory system comprising:

a nonvolatile memory; and

a controller circuit configured to:

receive a read request from the host apparatus;

on receiving the read request, perform a read processing until the read processing succeeds, the read processing including a first read operation and one or more second read operation, the first read operation including reading data from the nonvolatile memory with a first parameter, the second read operation including reading the data from the nonvolatile memory with a second parameter that is different from the first parameter; and

if a number of the first and second read operations exceeds a first threshold, output information about a life of the nonvolatile memory based on the number of the first and second read operations to cause the display device to display the life of the nonvolatile memory.

2. The memory system according to claim 1 , wherein

the controller further configured to:

compare the number of the first and second read operations with the first threshold, and

determine a degree of deterioration of the nonvolatile memory in accordance with a result of the comparing.

3. The memory system according to claim 1 , wherein

the nonvolatile memory includes a plurality of memory cells,

the controller further configured to:

monitor a number of bit errors in data in the plurality of memory cells in performing the first and second read operations, and

determine a degree of deterioration of the nonvolatile memory in accordance with a result of the monitoring.

4. The memory system according to claim 3 , wherein

the controller further configured to:

if the number of bit errors exceeds a second threshold, output information about the life of the nonvolatile memory based on the number of bit errors to cause the display device to display the life of the nonvolatile memory.

5. The memory system according to claim 1 , wherein

the nonvolatile memory includes a plurality of memory cells, and each of the plurality of memory cells is configured to store two or more than two bits of data.

6. The memory system according to claim 1 , wherein

the nonvolatile memory is a NAND type flash memory.

7. The memory system according to claim 1 , wherein

the nonvolatile memory includes a plurality of blocks, the plurality of blocks including a first block,

the controller further configured to:

if the number of the first and second read operations of the first block exceeds the first threshold, output information about the life of the nonvolatile memory and identifier of the first block based on the number of the first and second read operations of the first block to cause the display device to display the life of the nonvolatile memory and the identifier of the first block.

8. A method of controlling a memory system connectable to a host apparatus, the memory system including a nonvolatile memory, the host apparatus including a display device, the method comprising:

receiving a read request from the host apparatus;

on receiving the read request, performing a read processing until the read processing succeeds, the read processing including a first read operation and one or more second read operation, the first read operation including reading data from the nonvolatile memory with a first parameter, the second read operation including reading the data from the nonvolatile memory with a second parameter that is different from the first parameter; and

if the number of the first and second read operations exceeds a first threshold, outputting information about a life of the nonvolatile memory based on the number of the first and second read operations to cause the display device to display the life of the nonvolatile memory.

9. The method according to claim 8 , further comprising:

comparing the number of the first and second read operations with the first threshold; and

determining a degree of deterioration of the nonvolatile memory in accordance with a result of the comparing.

10. The method according to claim 8 , wherein

the nonvolatile memory includes a plurality of memory cells,

the method further comprising:

monitoring a number of bit errors in data in the plurality of memory cells in performing the first and second read operations, and

determining a degree of deterioration of the nonvolatile memory in accordance with a result of the monitoring.

11. The method according to claim 10 , further comprising:

if the number of bit errors exceeds a second threshold, outputting information about the life of the nonvolatile memory based on the number of bit errors to cause the display device to display the life of the nonvolatile memory.

12. The method according to claim 8 , wherein

the nonvolatile memory includes a plurality of memory cells, and each of the plurality of memory cells is configured to store two or more than two bits of data.

13. The method according to claim 8 , wherein

the nonvolatile memory is a NAND type flash memory.

14. The method according to claim 8 , wherein

the nonvolatile memory includes a plurality of blocks, the plurality of blocks including a first block,

the method further comprising:

if the number of the first and second read operations of the first block exceeds the first threshold, outputting information about the life of the nonvolatile memory and identifier of the first block based on the number of the first and second read operations of the first block to cause the display device to display the life of the nonvolatile memory and the identifier of the first block.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Jan 21, 2022
From: TOSHIBA MEMORY CORPORATION; K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058805/0696 →
CHANGE OF NAME Recorded Jan 21, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058805/0801 →