Charge to voltage converter

1. A charge to voltage (Q2V) converter for converting a charge to a voltage, the Q2V converter comprising:

a pair of push-pull source followers; and

a set of alternating current (AC) coupling capacitors coupled to each of the push-pull source followers.

2. The Q2V converter of claim 1 , further comprising:

a set of reset switches; wherein the set of AC coupling capacitors includes a trimmable capacitor enabled to change a capacitance of the set of AC coupling capacitors.

3. The Q2V converter of claim 1 , wherein the Q2V is connected to a set of successive-approximation-register (SAR) ADCs; wherein an output of the pair of push-pull source followers is used to drive the set of SAR ADCs.

4. The Q2V converter of claim 1 , further comprising a set of bootstrapped shields and an input node; wherein the bootstrapped shields are driven by an output node and electrically coupled to the input node and reduce an effective input capacitance of the Q2V converter.

5. The Q2V converter of claim 4 , further comprising:

a set of bias nodes;

a set of successive-approximation-register (SAR) input capacitors; and

logic enabling:

closing of the set of reset switches to reset values in the Q2V converter;

shorting bias nodes; and

electrically connecting the set of SAR input capacitors to the Q2V converter.

6. The Q2V converter of claim 5 , wherein the logic further comprises:

opening the set of reset switches of the Q2V converter;

integrating a current pulse into the Q2V converter; and

disconnecting the set of SAR input capacitors of the Q2V converter.

7. The Q2V converter of claim 6 , wherein the logic further comprises converting a received pulse into a voltage using the SAR input capacitors.

8. A method for converting a current pulse to a voltage, the method comprising:

closing a set of reset switches of a charge to voltage (Q2V) converter to reset values in the Q2V converter; wherein the Q2V converter comprises a set of bias nodes; and

shorting the set of bias nodes of the Q2V converter.

9. The method of claim 8 , further comprising:

connecting a set of successive-approximation-register (SAR) input capacitors of the Q2V converter;

opening the set of reset switches of the Q2V converter;

integrating a current pulse into the Q2V converter; and

disconnecting the set of SAR input capacitors of the Q2V converter.

10. The method of claim 9 , further comprising converting a received pulse into a voltage using the SAR input capacitors.

11. A system for converting charge to voltage, the system comprising:

a charge to voltage (Q2V) converter; wherein the Q2V converter comprises a set of reset switches, a set of successive-approximation-register (SAR) input capacitors, and a set of bias nodes; and

logic enabling the Q2V converter to:

close the set of reset switches to reset values in the Q2V converter;

short the set of bias nodes of the Q2V converter; and

connect the set of SAR input capacitors of the Q2V converter.

12. The system of claim 11 , wherein the logic further enables the Q2V converter to:

open the set of reset switches of the Q2V converter;

integrate a current pulse into the Q2V converter; and

disconnect the set of SAR input capacitors of the Q2V converter.

13. The system of claim 12 , wherein the logic further enables the Q2V converter to convert a received pulse into a voltage using the set of SAR input capacitors.

14. The system of claim 13 , where the Q2V converter further comprises a pair of push-pull source followers and a set of alternating current (AC) coupling capacitors.

15. The system of claim 14 , wherein each of the pair of push-pull source followers comprises a set of capacitors; wherein the set of capacitors includes a trimmable capacitor enabled to change the capacitance of the set of capacitors.

16. The system of claim 15 , further comprising:

a set of SAR analog-to-digital converters (ADCs); wherein the Q2V is connected to the set of SAR ADCs; wherein an output of the push-pull source followers is used to drive the set of ADCs.

17. The system of claim 16 , wherein the Q2V converter further comprises a set of bootstrapped shields and an input node; wherein the bootstrapped shields are driven by an output node and electrically coupled to the input node and reduce an effective input capacitance of the Q2V converter.

18. A method for converting a current pulse to a voltage, the method comprising:

closing a set of reset switches of a charge to voltage (Q2V) converter; wherein the Q2V converter comprises a set of bias nodes; and

shorting the set of bias nodes of the Q2V converter.

19. The method of claim 18 , further comprising connecting a set of successive-approximation-register (SAR) input capacitors of the Q2V converter.

20. The method of claim 19 , further comprising:

opening the set of reset switches of the Q2V converter; and

integrating a current pulse into the Q2V converter.